21150-AB Intel Corporation, 21150-AB Datasheet - Page 91

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
21150
When the last locked transaction is a posted write transaction, the 21150 deasserts s_lock_l on the
secondary bus at the end of the transaction because the lock was relinquished at the end of the write
transaction on the primary bus.
When the 21150 receives a target abort or a master abort in response to a locked delayed
transaction, the 21150 returns a target abort when the initiator repeats the locked transaction. The
initiator must then deassert p_lock_l at the end of the transaction. The 21150 sets the appropriate
status bits, flagging the abnormal target termination condition (see
Section
4.8). Normal
forwarding of unlocked posted and delayed transactions is resumed.
When the 21150 receives a target abort or a master abort in response to a locked posted write
transaction, the 21150 cannot pass back that status to the initiator. The 21150 asserts p_serr_l when
a target abort or a master abort is received during a locked posted write transaction, if the SERR#
enable bit is set in the command register. Signal p_serr_l is asserted for the master abort condition
if the master abort mode bit is set in the bridge control register (see
Section
7.4).
Preliminary
Datasheet
83

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