21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 94/164:

Secondary Arbiter Example

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21150
The secondary arbiter supports a programmable 2-level rotating algorithm. Two groups of masters
are assigned, a high priority group and a low priority group. The low priority group as a whole
represents one entry in the high priority group; that is, if the high priority group consists of n
masters, then in at least every n+1 transactions the highest priority is assigned to the low priority
group. Priority rotates evenly among the low priority group. Therefore, members of the high
priority group can be serviced n transactions out of n+1, while one member of the low priority
group is serviced once every n+1 transactions.
where four masters, including the 21150, are in the high priority group, and six masters are in the
low priority group. Using this example, if all requests are always asserted, the highest priority
rotates among the masters in the following fashion (high priority members are given in italics, low
priority members, in boldface type):
B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, and so
on.
Figure 18. Secondary Arbiter Example
Each bus master, including the 21150, can be configured to be in either the low priority group or
the high priority group by setting the corresponding priority bit in the arbiter control register in
device-specific configuration space. Each master has a corresponding bit. If the bit is set to 1, the
master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low
priority group. If all the masters are assigned to one group, the algorithm defaults to a straight
rotating priority among all the masters. After reset, all external masters are assigned to the low
priority group, and the 21150 is assigned to the high priority group. The 21150 receives highest
priority on the target bus every other transaction, and priority rotates evenly among the other
masters.
Priorities are reevaluated every time s_frame_l is asserted, that is, at the start of each new
transaction on the secondary PCI bus. From this point until the time that the next transaction starts,
the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If
a grant for a particular request is asserted, and a higher priority request subsequently asserts, the
arbiter deasserts the asserted grant signal and asserts the grant corresponding to the new higher
priority request on the next PCI clock cycle. When priorities are reevaluated, the highest priority is
assigned to the next highest priority master relative to the master that initiated the previous
transaction. The master that initiated the last transaction now has the lowest priority in its group.
If the 21150 detects that an initiator has failed to assert s_frame_l after 16 cycles of both grant
assertion and a secondary idle bus condition, the arbiter deasserts the grant. That master does not
receive any more grants until it deasserts its request for at least one PCI clock cycle.
86
Figure 18
shows an example of an internal arbiter
m2
lpg
m1
B
m0
Note:
m8
B – 21150
m x – Bus Master Number
lpg – Low Priority Group
Arbiter Control Register = 10 0000 0111b
m3
m4
m5
m6
m7
LJ-04643.AI4
Preliminary
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