21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Bus Parking

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To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant
signal in the same PCI cycle in which it deasserts another. It deasserts one grant, and then asserts
the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is,
either s_frame_l or s_irdy_l is asserted, the arbiter can deassert one grant and assert another grant
during the same PCI clock cycle.
9.2.2
Secondary Bus Arbitration Using an External Arbiter
The internal arbiter is disabled when the secondary bus central function control pin, s_cfn_l, is
pulled high. An external arbiter must then be used.
When s_cfn_l is tied high, the 21150 reconfigures two pins to be external request and grant pins.
The s_gnt_l<0> pin is reconfigured to be the 21150’s external request pin because it is an output.
The s_req_l<0> pin is reconfigured to be the external grant pin because it is an input. When an
external arbiter is used, the 21150 uses the s_gnt_l<0> pin to request the secondary bus. When the
reconfigured s_req_l<0> pin is asserted low after the 21150 has asserted s_gnt_l<0>, the 21150
initiates a transaction on the secondary bus one cycle later. If s_req_l<0> is asserted and the 21150
has not asserted s_gnt_l<0>, the 21150 parks the s_ad, s_cbe_l, and s_par pins by driving them to
valid logic levels.
The unused secondary bus grant outputs, s_gnt_l<8:1>, are driven high. Unused secondary bus
request inputs, s_req_l<8:1>, should be pulled high.
9.2.3

Bus Parking

Bus parking refers to driving the AD, C/BE#, and PAR lines to a known value while the bus is idle.
In general, the device implementing the bus arbiter is responsible for parking the bus or assigning
another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted,
and the device’s request is not asserted. The AD and C/BE# signals should be driven first, with the
PAR signal driven one cycle later.
The 21150 parks the primary bus only when p_gnt_l is asserted, p_req_l is deasserted, and the
primary PCI bus is idle. When p_gnt_l is deasserted, the 21150 tristates the p_ad, p_cbe_l, and
p_par signals on the next PCI clock cycle. If the 21150 is parking the primary PCI bus and wants to
initiate a transaction on that bus, then the 21150 can start the transaction on the next PCI clock
cycle by asserting p_frame_l if p_gnt_l is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last
master that used the PCI bus. That is, the 21150 keeps the secondary bus grant asserted to a
particular master until a new secondary bus request comes along. After reset, the 21150 parks the
secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter
is disabled, the 21150 parks the secondary bus only when the reconfigured grant signal,
s_req_l<0>, is asserted and the secondary bus is idle.
Preliminary
Datasheet
21150
87