21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 98/164:

Secondary Clock Control

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21150
10.2

Secondary Clock Control

The 21150 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data
stream is shifted into the secondary clock control register and is used for selectively disabling
secondary clock outputs.
The serial data stream is shifted in as soon as p_rst_l is detected deasserted and the secondary reset
signal, s_rst_l, is detected asserted. The deassertion of s_rst_l is delayed until the 21150 completes
shifting in the clock mask data, which takes 23 clock cycles. After that, the gpio pins can be used as
general-purpose I/O pins.
An external shift register should be used to load and shift the data. The gpio pins are used for shift
register control and serial data input.
Table 32. gpio Operation
gpio Pin
gpio<0>
gpio<1>
gpio<2>
gpio<3>
The data is input through the dedicated input signal, msk_in.
The shift register circuitry is not necessary for correct operation of the 21150. The shift registers
can be eliminated, and msk_in can be tied low to enable all secondary clock outputs or tied high to
force all secondary clock outputs high.
Table 33
shows the format of the serial stream.
Table 33. gpio Serial Data Format
Bit
<1:0>
<3:2>
<5:4>
<7:6>
<8>
<9>
<10>
<11>
<12>
<13>
<14>
<15>
90
Table 32
shows the operation of the gpio pins.
Operation
Shift register clock output at 33 MHz maximum frequency
Not used
Shift register control
0—Load
1—Shift
Not used
Description
Slot 0 PRSNT#<1:0> or device 0
Slot 1 PRSNT#<1:0> or device 1
Slot 2 PRSNT#<1:0> or device 2
Slot 3 PRSNT#<1:0> or device 3
Device 4
Device 5
Device 6
Device 7
Device 8
21150 s_clk input
Reserved
Reserved
s_clk_o Output
0
1
2
3
4
5
6
7
8
9
Not applicable
Not applicable
Preliminary
Datasheet