RTL8110S-32 REALTEK, RTL8110S-32 Datasheet
RTL8110S-32
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... RTL8110S-32/RTL8110S-64 INTEGRATED GIGABIT ETHERNET CONTROLLER (LOM) DATASHEET Rev. 1.4 24 September 2003 Track ID: JATR-1076-21 ...
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... This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT This document is intended for use by the software engineer when programming for Realtek RTL8110S-32 & RTL8110S-64 controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document ...
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... S 5.8. P & G ................................................................................................................................................... 11 OWER ROUND 5. ............................................................................................................................................. 11 OT ONNECTED 6. FUNCTIONAL DESCRIPTION ...................................................................................................................................... 12 6.1. T ............................................................................................................................................................ 12 RANSCEIVER 6.1.1. Transmitter........................................................................................................................................................... 12 6.1.2. Receiver ............................................................................................................................................................... 12 6.2. MAC ......................................................................................................................................................................... 12 6. ................................................................................................................................................................ 13 EXT AGE 6.4. MII/GMII I ............................................................................................................................................... 13 NTERFACE 6.4.1. MII ....................................................................................................................................................................... 13 6.4.2. GMII .................................................................................................................................................................... 13 Integrated Gigabit Ethernet Controller Table of Contents ................................................................................................................................. 3 ............................................................................................................................ 4 .............................................................................................................................. 5 SOLATION ........................................................................................................................................... 9 ....................................................................................................................................... 10 iii RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... PERATION IMING 7.7.1. PCI Bus Timing Parameters ................................................................................................................................ 24 7.7.2. PCI Clock Specification....................................................................................................................................... 26 7.7.3. PCI Transactions ................................................................................................................................................. 27 8. MECHANICAL DIMENSIONS....................................................................................................................................... 42 8.1. 128-P QFP M IN ECHANICAL 8.2. 233-PIN TFBGA M ECHANICAL 9. ORDERING INFORMATION ......................................................................................................................................... 46 Integrated Gigabit Ethernet Controller ................................................................................................................................ 21 ATINGS C ................................................................................................................. 21 ONDITIONS .......................................................................................................................................... 21 .................................................................................................................................... 22 .................................................................................................................................... 24 D ................................................................................................................. 42 IMENSIONS D ........................................................................................................... 44 IMENSIONS iv RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... ARAMETERS T 18 ABLE EASUREMENT ONDITION T 19 ABLE LOCK AND ESET PECIFICATIONS T 20 ABLE RDERING NFORMATION Integrated Gigabit Ethernet Controller List of Tables ............................................................................................................................. 5 SOLATION ........................................................................................................................................... 9 ...................................................................................................................................... 10 ............................................................................................................................... 21 ATINGS C ................................................................................................................ 21 ONDITIONS ......................................................................................................................................... 21 ................................................................................................................................... 22 ............................................................................................................................................. 22 P ................................................................................................................. 23 ARAMETERS ................................................................................................................................. 24 P ............................................................................................................... 25 ARAMETERS ......................................................................................................................... 26 ......................................................................................................................................... 46 v RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... BIT ADDRESS BIT DATA TRANSFER GRANTED 4GB (DAC, 64- , 32- BIT ADDRESS 4GB (DAC, 64- , 64- BIT ADDRESS BIT DATA TRANSFER GRANTED 4GB (DAC, 64- , 64- BIT ADDRESS vi RTL8110S-32/RTL8110S-64 ; 32- ) .......................................................... 29 BIT SLOT ; 32- )......................................................... 30 BIT SLOT ; 64- BIT SLOT ; 64- BIT SLOT ; 64- BIT SLOT ; 64- BIT SLOT ...
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... PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To better qualify as a server card, the RTL8110S-32 and RTL8110S-64 support the PCI Dual Address Cycle (DAC) command when the assigned buffers reside at a physical memory address higher than 4 Gigabytes. ...
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... Supports Full Duplex flow control (IEEE 802.3x) 3. System Applications Gigabit Ethernet on Motherboard. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Supports IEEE 802.1Q VLAN tagging Serial EEPROM 3.3V signaling, 5V PCI I/O tolerant ...
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... VDD33 GND SERRB 76 PAR 77 CBEB1 78 VDD18 79 PCIAD15 80 GND 81 VSSPST 82 PCIAD14 83 PCIAD13 Integrated Gigabit Ethernet Controller RTL8110S-32 Figure 1. 128-Pin QFP Pin Assignments 3 RTL8110S-32/RTL8110S-64 Datasheet 19 MDI3- 18 MDI3+ 17 VSS 16 AVDDL 15 MDI2- 14 MDI2+ 13 VSS AVDDH 9 VSS 8 CTRL25 7 AVDDL 6 MDI1- 5 MDI1+ ...
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... TFBGA Pin Assignments Integrated Gigabit Ethernet Controller RTL8110S-64 Figure 2. 233-Pin TFBGA Pin Assignments 4 RTL8110S-32/RTL8110S- Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... The default output is an active high signal. Once a PME event is received, the LANWAKE and PMEB assert at the same time when the LWPME (bit4, CONFIG4) is set the LWPME is set to 1, the LANWAKE asserts only when the PMEB asserts and ISOLATEB is low. 5 RTL8110S-32/RTL8110S-64 LWACT Active high ...
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... During the data phase, CBEBPIN3-0 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. CBEBPIN0 applies to byte 0, and CBEBPIN3 applies to byte 3. 6 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low target, this signal indicates that the master has put data on the bus. 7 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... ACK64B has the same timing as DEVSELB. L2 Request 64-bit Transfer: When asserted by the current bus master, indicates it desires to transfer data using 64 bits. REQ64B also has the same timing as FRAMEB. 8 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair MDI crossover mode, this pair acts as the BI_DD+/- pair MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair MDI crossover mode, this pair acts as the BI_DC+/- pair. 9 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Reference. External Resistor Reference. Table 7. LEDs Pin No Description (233BGA) C10 LEDS 00 1-0 D10 C11 LED0 Tx/Rx D9 LINK LED1 100 LINK LED2 10 LINK LED3 1000 10 RTL8110S-32/RTL8110S- LINK10/ ACT(Tx/Rx) Tx LINK10/100/ LINK10/100 LINK100/ 1000 /1000 FULL Rx LINK1000/ - FULL Track ID: JATR-1076-21 Datasheet 11 ACT ACT FULL ACT Rev. 1.4 ...
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... F4, G4, C4, D5, Analog Ground 124, 128 D6, D7, E3 Table 9. NC (Not Connected) Pin No Description (233BGA) A1, A2, A3, A4, A7, Not Connected. A8, A9, A10, A14, A16, B1, B2, B4, B5, B6, B7, B8, B9, B14, B15, C1, C13, C15, F2, F3, K1, L1, N3, N17, P1, P15, U1, U10 11 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... The RTL8110S will automatically pad any packets less than 64 bytes to 64-bytes long (including a 4-byte CRC) before transmitting that packet onto the network medium packet consists of two or more descriptors, then the descriptors in command mode should have the same configuration, except EOR, FS, LS bits. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 12 Track ID: JATR-1076-21 Datasheet ...
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... PHY. 6.4.2. GMII In 1000Base-T mode, the GMII interface is selected, the 125MHz transmit clock is expected on GTXCLK, TXCLK sources 25MHz, 2.5MHz, or 0MHz clock depending on the operation mode, and RXCLK sources the 125MHz receive clock. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 13 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... LED pin is driven low. Once disconnected, the link LED pin is driven high indicating that no network connection exists. 6.5.2. RX LED In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 Power On LED = High Receiving Packet? Yes ...
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... TX LED In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Integrated Gigabit Ethernet Controller Power On LED = High Transmitting Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 4. TX LED 15 RTL8110S-32/RTL8110S-64 Datasheet No Track ID: JATR-1076-21 Rev. 1.4 ...
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... TX/RX LED In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Integrated Gigabit Ethernet Controller Power On LED = High Tx/Rx Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 5. TX/RX LED 16 RTL8110S-32/RTL8110S-64 Datasheet No Track ID: JATR-1076-21 Rev. 1.4 ...
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... RTL8110S initialization uses default values for the appropriate Configuration and Operational Registers. Integrated Gigabit Ethernet Controller Power On LED = High No Link? Yes LED = Low No Tx/Rx packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 6. LINK/ACT LED 17 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... This pin should be connected to Boot PROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8110S assumes that no Aux. Power exists. Output data bus 18 RTL8110S-32/RTL8110S-64 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... CRC: The RTL8110S supports two normal wakeup frames (covering 64 mask bytes from offset any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 19 Track ID: JATR-1076-21 Datasheet ...
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... LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low. LWAKE is asserted whenever a wakeup event occurs. 2. Bit1 of DELAY byte (offset 1Fh, EEPROM): LWAKE signal is enabled. LWAKE signal is disabled. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 20 Track ID: JATR-1076-21 Datasheet . There is no hardware cold ...
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... Drive Level Integrated Gigabit Ethernet Controller Table 11. Absolute Maximum Ratings Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -55 Table 12. Recommended Operating Conditions Pins Minimum VDD33, 3.0 AVDDH VDD25 2.25 VDD18 1.67 0 Table 13. Crystal Requirements Description/Condition =25℃ RTL8110S-32/RTL8110S-64 Maximum VDD33 + 0.5 VDD33 + 0.5 +125 Typical Maximum 3.3 3.6 2.5 2.75 1.8 1.92 70 125 Minimum Typical Maximum 25 -50 +50 -30 +30 ...
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... Integrated Gigabit Ethernet Controller Table 14. Thermal Characteristics Minimum -55 0 Table 15. DC Characteristics Conditions Minimum 3.0 1.67 2. -8mA 0.9 * Vcc 8mA 0.5 * Vcc -0 -1.0 GND V out = -10 GND 22 RTL8110S-32/RTL8110S-64 Datasheet Maximum Units +125 Typical Maximum Units 3.3 3.6 1.8 1.92 2.5 2.75 Vcc 0.1 * Vcc Vcc+0.5 0.3 * Vcc 1.0 10 ...
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... A0 Dn tsk tskh tskl tdih tdos STATUS VALID Figure 7. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters EEPROM Type 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 23 RTL8110S-32/RTL8110S- tcs ... D0 BUSY twp tcsh tdoh Min. Max. 1000/250 10/10 4/1 1000/500 1000/250 ...
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... Table 17. PCI Bus Timing Parameters 66MHz Min Max 100 40 10*Tcyc RTL8110S-32/RTL8110S-64 Datasheet Min. Max. Unit 400/50 ns 400/100 ns 2000/500 ns 2000/500 ns 1000/500 ns 33MHz Min Symbol Parameter ...
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... V_test inputs valid V_tl Input Timing Measurement Conditions Table 18. Measurement Condition Parameters Level Vth 0.6Vcc 0.2Vcc Vtf 0.4Vcc Vtest Vtrise 0.285Vcc Vtfall 0.615Vcc Vmax 0.4Vcc 25 RTL8110S-32/RTL8110S-64 V_th V_tl V_th V_test V_tl T_h V_test V_max Units V/ns Track ID: JATR-1076-21 Datasheet Rev ...
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... Figure 10. 3.3V Clock Waveform T_skew V_ih T_skew V_il Figure 11. Clock Skew Diagram Table 19. Clock and Reset Specifications 66MHz Min Max 1 RTL8110S-32/RTL8110S-64 0.4Vcc, peak-to-peak (minimum) V_test T_skew V_test 33MHz Min Symbol Parameter 30 ∞ mV/ns 2 Track ID: JATR-1076-21 ...
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... BUS CMD IRDYB TRDYB DEVSELB CLK 1 FRAMEB AD31-0 ADDRESS C/BE3-0B BUS CMD IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller DATA BE3-0B Figure 12. I/O Read DATA BE3-0B Figure 13. I/O Write 27 RTL8110S-32/RTL8110S- Track ID: JATR-1076-21 Datasheet 10 10 Rev. 1.4 ...
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... DEVSELB CLK 1 FRAMEB IDSEL AD31-0 ADDRESS C/BE3-0B BUS CMD IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller DATA BE3-0B Figure 14. Configuration Read DATA BE3-0B Figure 15. Configuration Write 28 RTL8110S-32/RTL8110S- Track ID: JATR-1076-21 Datasheet 10 10 Rev. 1.4 ...
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... Figure 17. Memory Read below 4GB (32-bit address, 32-bit data; 32-bit slot) Integrated Gigabit Ethernet Controller ADDRESS DATA ADDRESS Figure 16. Bus Arbitration DATA-1 ADDRESS BE3-0B BUS CMD 29 RTL8110S-32/RTL8110S- DATA DATA-2 DATA-3 Track ID: JATR-1076-21 Datasheet 10 9 Rev. 1.4 ...
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... Figure 18. Memory Write below 4GB (32-bit address, 32-bit data; 32-bit slot) CLK 1 FRAMEB IRDYB TRDYB STOPB DEVSELB Figure 19. Target Initiated Termination - Disconnect Integrated Gigabit Ethernet Controller ADDRESS DATA-1 DATA-2 BUS CMD BE3-0B-1 BE3-0B RTL8110S-32/RTL8110S-64 Datasheet DATA-3 BE3-0B Track ID: JATR-1076-21 Rev. 1.4 ...
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... TRDYB STOPB DEVSELB CLK 1 FRAMEB IRDYB TRDYB DEVSELB Integrated Gigabit Ethernet Controller Figure 20. Target Initiated Termination - Abort FAST MED SLOW Figure 21. Master Initiated Termination - Abort 31 RTL8110S-32/RTL8110S- RESPONSE SUB ACKNOWLEDGE Track ID: JATR-1076-21 Datasheet 8 9 Rev. 1.4 ...
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... CLK 2 1 FRAMEB AD ADDRESS C/BE# BUS CMD PAR/PAR64 SERR# PERR# Integrated Gigabit Ethernet Controller DATA ADDRESS BE# BUS CMD Figure 22. Parity Operation – One Example 32 RTL8110S-32/RTL8110S- DATA BE# Track ID: JATR-1076-21 Datasheet 10 Rev. 1.4 ...
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... C/BE3-0B C/BE7-4B IRDYB TRDYB DEVSELB ACK64B Figure 23. Memory Read Below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller DATA-1 ADDRESS BE3-0B BUS CMD BE7-4B 33 RTL8110S-32/RTL8110S- DATA-2 DATA-3 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... TRDYB DEVSELB ACK64B Figure 24. Memory Write below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller ADDRESS DATA-1 DATA-2 DATA-2 BUS CMD BE3-0B-1 BE3-0B-2 BE7-4B-1 34 RTL8110S-32/RTL8110S-64 Datasheet DATA-3 BE3-0B-3 Track ID: JATR-1076-21 Rev. 1.4 ...
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... TRDYB DEVSELB ACK64B Figure 25. Memory Read below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller DATA-1 ADDRESS DATA-2 BE3-0B BUS CMD BE7-4B 35 RTL8110S-32/RTL8110S- DATA-3 DATA-5 DATA-4 DATA-6 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... Figure 26. Memory Write below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller ADDRESS DATA-1 DATA-3 DATA-2 DATA-4 BUS CMD BE3-0B-1 BE3-0B-2 BE7-4B-1 BE7-4B-2 36 RTL8110S-32/RTL8110S-64 Datasheet DATA-5 DATA-6 BE3-0B-3 BE7-4B-3 Track ID: JATR-1076-21 Rev. 1.4 ...
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... Figure 28. Memory Write above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot) Integrated Gigabit Ethernet Controller HI-ADDR DATA-1 BUS CMD HI-ADDR DATA-1 DATA-2 BUS CMD BE3-0B-1 BE3-0B-2 37 RTL8110S-32/RTL8110S- DATA-2 DATA-3 BE3- DATA-3 BE3-0B-3 Track ID: JATR-1076-21 Datasheet 10 10 ...
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... DEVSELB ACK64B Figure 29. Memory Read above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller HI-ADDR DATA-1 HI-ADDR BUS CMD BUS CMD BE7-4B 38 RTL8110S-32/RTL8110S- DATA-2 DATA-3 BE3-0B Track ID: JATR-1076-21 Datasheet 10 Rev. 1.4 ...
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... Figure 30. Memory Write above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller HI-ADDR DATA-1 DATA-2 HI-ADDR DATA-2 BUS CMD BE3-0B-1 BE3-0B-2 BUS CMD BE7-4B-1 39 RTL8110S-32/RTL8110S- DATA-3 BE3-0B-3 Track ID: JATR-1076-21 Datasheet 10 Rev. 1.4 ...
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... Figure 31. Memory Read above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller HI-ADDR DATA-1 HI-ADDR DATA-2 BUS CMD BUS CMD 40 RTL8110S-32/RTL8110S- DATA-3 DATA-5 DATA-4 DATA-6 BE3-0B BE7-4B Track ID: JATR-1076-21 Datasheet 10 Rev ...
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... Figure 32. Memory Write above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot) Integrated Gigabit Ethernet Controller HI-ADDR DATA-1 DATA-3 HI-ADDR DATA-2 DATA-4 BUS CMD BE3-0B-1 BE3-0B-2 BUS CMD BE7-4B-1 BE7-4B-2 41 RTL8110S-32/RTL8110S- DATA-5 DATA-6 BE3-0B-3 BE7-4B-3 Track ID: JATR-1076-21 Datasheet 10 Rev. 1.4 ...
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... Mechanical Dimensions 8.1. 128-Pin QFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 42 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... Dimension b does not include dambar rotrusion/intrusion. 0.10 0.25 0.91 3. Controlling dimension: Millimeter 2.60 2.85 3.10 4. General appearance spec. Should be based on final 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.00 20.25 0.25 0.5 0.75 16.90 17.20 17.50 APPROVE 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0° - 12° REALTEK SEMICONDUCTOR CO., LTD 43 RTL8110S-32/RTL8110S-64 Datasheet visual inspection. TITLE: -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. Q128 - 1 DATE Track ID: JATR-1076-21 Rev. 1.4 ...
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... TFBGA Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 44 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... Notes for 233-Pin TFBGA Dimensions Integrated Gigabit Ethernet Controller RTL8110S-32/RTL8110S-64 45 Track ID: JATR-1076-21 Datasheet Rev. 1.4 ...
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... RTL8110S-64 Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw Integrated Gigabit Ethernet Controller Table 20. Ordering Information Package 128-pin QFP 233-pin TFBGA 46 RTL8110S-32/RTL8110S-64 Datasheet Status Track ID: JATR-1076-21 Rev. 1.4 ...