CS8952CQ Cirrus Logic, Inc., CS8952CQ Datasheet
CS8952CQ
Related parts for CS8952CQ
CS8952CQ Summary of contents
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... MLT-3 Descrambler Decoder Decoder Manchester Decoder MII Link Timing Control/Status Management Recovery Registers Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS8952 “Ordering Information” on page 80. 10/100 10BaseT Filter M TX+, U TX- X Slew Rate Control TX_NRZ+, ECL Driver TX_NRZ- ...
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TABLE OF CONTENTS 1. SPECIFICATIONS AND CHARACTERISTICS......................................................... 3 2. INTRODUCTION ..................................................................................................... 18 2.1 High Performance Analog ............................................................................. 18 2.2 Low Power Consumption .............................................................................. 18 2.3 Application Flexibility..................................................................................... 18 2.4 Typical Connection Diagram ......................................................................... 18 3. FUNCTIONAL DESCRIPTION ................................................................................ 18 3.1 ...
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SPECIFICATIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Input Current Input Voltage Ambient Temperature Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these ...
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DC CHARACTERISTICS Parameter External Oscillator XTAL_I Input Low Voltage XTAL_I Input High Voltage XTAL_I Input Low Current XTAL_I Input High Current XTAL_I Input Capacitance XTAL_I Input Cycle Time XTAL_I Input Low Time XTAL_I Input High Time Power Supply Power Supply ...
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DC CHARACTERISTICS Parameter Output High Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK Input Low Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Input High Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Tri-Level Input Voltages AN[1:0], TCM, ...
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CHARACTERISTICS Parameter 10BASE-T Interface Transmitter Differential Output Voltage (Peak) Receiver Normal Squelch Level (Peak) Receiver Low Squelch Level (LoRxSquelch bit set) 10BASE-T Transmitter TXD Pair Jitter into 100 Ω Load TXD Pair Return to ≤ after Last ...
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CHARACTERISTICS Parameter 100BASE-TX Transmitter TX Differential Output Voltage (Peak) Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Symmetry Duty Cycle Distortion Overshoot/Undershoot Transmit Jitter TX Differential Output Impedance 100BASE-TX Receiver Receive Signal Detect Assert Threshold Receive Signal Detect De-assert Threshold ...
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MII RECEIVE TIMING - 4B/5B ALIGNED MODES Parameter RX_CLK Period RX_CLK Pulse Width RXD[3:0],RX_ER/RXD4,RX_DV setup to rising edge of RX_CLK RXD[3:0],RX_ER/RXD4,RX_DV hold from rising edge of RX_CLK CRS to RXD latency “Start of Stream” to CRS asserted “End of ...
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MII RECEIVE TIMING - 5B BYPASS ALIGN MODE Parameter RX_CLK Period RX_CLK Pulse Width RXD[4:0] setup to rising edge of RX_CLK RXD[4:0] hold after rising edge of RX_CLK Start of 5B symbol to symbol output on RX[4:0] RX Symbol ...
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MII TRANSMIT TIMING - 4B/5B ALIGN MODES Parameter TXD[3:0] Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN “high” to CRS asserted latency ...
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MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE Parameter TXD[4:0] Setup to TX_CLK High TXD[4:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TXD[4:0] Sampled to TX+/- output (TX Latency) TX_CLK t t SU1 HD1 Data TXD[4:0] IN ...
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MII RECEIVE TIMING Parameter RX_CLK Period RX_CLK Pulse Width RXD[3:0], RX_ER, RX_DV setup to rising edge of RX_CLK RXD[3:0], RX_ER, RX_DV hold from rising edge of RX_CLK RX data valid from CRS RX+/- preamble to CRS asserted RX+/- end ...
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MII TRANSMIT TIMING Parameter TXD[3:0] Setup to TX_CLK High TX_ER Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN “high” to CRS asserted ...
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SERIAL RECEIVE TIMING Parameter RX+/- active to RXD[0] active RX+/- active to CRS active RXD[0] setup from RX_CLK RXD[0] hold from RX_CLK RX_CLK hold after CRS off RXD[0] throughput delay CRS turn off delay RX+/- t CRS CRS RX_CLK ...
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SERIAL TRANSMIT TIMING Parameter TX_EN Setup from TX_CLK TX_EN Hold after TX_CLK TXD[0] Setup from TX_CLK TXD[0] Hold after TX_CLK Transmit start-up delay Transmit throughput delay TX_CLK t EHCH TX_EN t DSCH TXD[0] t STUD TX+/- CrystalLAN™ 100BASE-X and ...
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AUTO NEGOTIATION / FAST LINK PULSE TIMING Parameter FLP burst to FLP burst FLP burst width Clock/Data pulses per burst Clock/Data pulse width Clock pulse to Data pulse Clock pulse to clock pulse TX+/- Clock Pulse TX+/- ...
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SERIAL MANAGEMENT INTERFACE TIMING Parameter MDC Period MDC Pulse Width MDIO Setup to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO valid (MDIO as output) CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol Min t ...
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INTRODUCTION The CS8952 is a complete physical-layer transceiv- er for 100BASE-TX and 10BASE-T applications. Additionally, the CS8952 can be used with an ex- ternal optical module for 100BASE-FX. 2.1 High Performance Analog The highly integrated mixed-signal design of the ...
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VDD_MII 25 MHz 4.7 kΩ 4.7 kΩ 1.5 kΩ XTAL_I XTAL_O MDIO MDC 4 TXD TX_ER/TXD[4] TX_EN 33 Ω TX_CLK MII 33 Ω I/F RX_CLK 33 Ω RXD[0] 33 Ω RXD[1]/PHYAD[1] 33 Ω RXD[2] 33 Ω RXD[3]/PHYAD[3] 33 Ω RX_ER/RXD[4]/PHYAD[4] ...
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CS8952, eliminating the need for the system to poll the CS8952 for state changes. The RX_EN signal allows the receiver outputs to be electrically isolated. The ...
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DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name 5-bit Symbol 2 10100 3 10101 4 01010 5 01011 6 01110 7 01111 8 10010 9 10011 A 10110 B 10111 C 11010 D 11011 E 11100 ...
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Name 5-bit Symbol V6 01000 V7 01100 V8 10000 V9 11001 1. CONTROL code groups become violations when found in the data portion of the frame. 2. Invalid code groups are mapped to 5h unless the Code Error Report select ...
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RX_CLK, RX_DV, COL, and CRS) onto a shared, external repeater system bus. 3.1.3 10BASE-T MII Application The digital interface used in this mode is the same as that used in the 100BASE-X MII mode except that TX_CLK and RX_CLK are ...
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Manchester Encoder and Decoder. Selection is made via: - setting bit 14 in the Basic Mode Control Register (address 00h setting bits 8 and 11 in the Loopback, By- pass, and Receiver Error Mask Register (address 18h) or ...
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AN1 AN0 Forced/ Auto Low Floating Forced High Floating Forced Floating Low Forced Floating High Forced Floating Floating Auto-Neg Low Low Auto-Neg Low High Auto-Neg High Low Auto-Neg High High Auto-Neg Table 5. Auto-Negotiation encapsulates information within a burst of ...
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STATUS Pins - COL - Collision indication, valid only for half duplex modes. - CRS - Carrier Sense indication SERIAL MANAGEMENT Pins - MDIO - a bi-directional serial data path - MDC - clock for MDIO (16.7 MHz max) - ...
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RXD[3:0] synchronously with respect to RX_CLK. Receive errors are indicated during frame reception by the assertion of RX_ER. It indicates that an error was detected somewhere in the frame currently be- ing transferred across the MII. RX_ER will transi- ...
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TX_CLK TX_EN TXD[3:0] Preamble/SFD TX_ER TX_CLK TX_EN TXD[3:0] Preamble/SFD TX_ER specification, while the remaining registers provide enhanced monitoring and control capabilities. As many as 31 devices may share a single Manage- ment Interface. A unique five-bit PHY address is associated ...
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A read transaction is indicated by an Opcode of 10 and a write by 01. The PHY Address is five bits, with the most signif- icant bit sent first. If the PHY address included in the frame is not 00000 ...
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CS8952 REGISTERS The CS8952 register set is comprised of the 16-bit status and control registers described below. A de- tailed description each register follows. Register Address 0h Basic Mode Control Register 1h Basic Mode Status Register 2h PHY Identifier ...
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Basic Mode Control Register - Address 00h 15 14 Software Speed Loopback Reset Selection 7 6 Collision Test BIT NAME TYPE 15 Software Reset Read/Set 14 Loopback Read/Write 0 13 Speed Selection Read/Write If auto-negotiation 12 Auto-Neg Enable Read/Write ...
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BIT NAME TYPE 9 Restart Auto-Neg Read/Set 8 Duplex Mode R/W 7 Collision Test R/W 6:0 Reserved Read Only 000 0000 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET 0 Setting this bit causes auto-negotiation to be restarted ...
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Basic Mode Status Register - Address 01h 15 14 100BASE-TX/ 100BASE-TX/ 100BASE-T4 Full Duplex Half Duplex Preamble Auto-Neg Reserved Suppression Complete BIT NAME TYPE 15 100BASE-T4 Read Only 0 14 100BASE-TX/Full Read Only 1 Duplex 13 ...
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BIT NAME TYPE 3 Auto-Neg Ability Read Only 1 2 Link Status Read Only 0 1 Jabber Detect Read Only 0 0 Extended Capability Read Only 1 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET DESCRIPTION This bit indicates that the ...
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PHY Identifier, Part 1 - Address 02h BIT NAME TYPE 15:0 Organizationally Read/Write 001Ah Unique Identifier (bits 3:18) CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Organizationally Unique Identifier: Bits[3:10 Organizationally ...
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PHY Identifier, Part 2 - Address 03h 15 14 Organizationally Unique Identifier - Bits[19:24 Part Number BIT NAME TYPE 15:10 Organizationally Read/Write 00 1000 Unique Identifier (bits 19:24) 9:4 Part Number Read/Write 10 0000 3:0 Revision Number ...
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Auto-Negotiation Advertisement Register - Address 04h 15 14 Next Page Acknowledge Remote Fault 7 6 Technology Ability Field BIT NAME TYPE 15 Next Page Read/Write 0 14 Acknowledge Read Only 0 13 Remote Fault Read/Write 0 12:5 Technology Ability ...
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Auto-Negotiation Link Partner Ability Register - Address 05h 15 14 Next Page Acknowledge Remote Fault 7 6 Technology Ability Field BIT NAME TYPE 15 Next Page Read Only 0 14 Acknowledge Read Only 0 13 Remote Fault Read Only ...
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Auto-Negotiation Expansion Register - Address 06h Reserved BIT NAME TYPE 15:5 Reserved Read Only 000 0000 0000 4 Parallel Detection Read Only 0 Fault 3 Link Partner Next Read Only 0 Page Able 2 Next ...
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Auto-Negotiation Next-Page Transmit Register - Address 07h 15 14 Next Page Acknowledge Message Page Acknowledge BIT NAME TYPE 15 Next Page Read/Write 0 14 Acknowledge Read Only 0 13 Message Page Read/Write 1 12 Acknowledge 2 ...
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Interrupt Mask Register - Address 10h 15 14 CIM Link Link Status Descrambler Unstable Change Lock Change 7 6 Reset Jabber Auto-Neg Complete Detect Complete This register indicates which events will cause an interrupt event on the MII_IRQ pin. ...
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BIT NAME TYPE 11 DCR Rollover Read/Write 0 10 FCCR Rollover Read/Write 0 9 RECR Rollover Read/Write 0 8 Remote Loopback Read/Write 0 Fault 7 Reset Complete Read/Write 1 6 Jabber Detect Read/Write 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 ...
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BIT NAME TYPE 5 Auto-Neg Complete Read/Write 0 4 Parallel Detection Read/Write 0 Fault 3 Parallel Fail Read/Write 0 2 Remote Fault Read/Write 0 1 Page Received Read/Write 0 0 Reserved Read Only 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 ...
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Interrupt Status Register - Address 11h 15 14 CIM Link Link Status Descrambler Unstable Change Lock Change 7 6 Reset Jabber Auto-Neg Complete Detect Complete This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All ...
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BIT NAME TYPE 8 Remote Loopback Read Only 0 Fault 7 Reset Complete Read Only 0 6 Jabber Detect Read Only 0 5 Auto-Neg Complete Read Only 0 4 Parallel Detection Read Only 0 Fault 3 Parallel Fail Read Only ...
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BIT NAME TYPE 2 Remote Fault Read Only 0 1 Page Received Read Only 0 0 Reserved Read Only 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET DESCRIPTION When auto-negotiation is enabled, this bit is set if the Remote Fault ...
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Disconnect Count Register - Address 12h BIT NAME TYPE 15:0 Disconnect Counter Read/Write 0000h CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Disconnect Counter Disconnect Counter RESET This field contains a ...
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False Carrier Count Register - Address 13h BIT NAME TYPE 15:0 False Carrier Read Only 0000h Counter CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 False Carrier Counter False Carrier Counter ...
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Scrambler Key Initialization Register - Address 14h 15 14 Load 7 6 BIT NAME TYPE 15 Load Read/Set 14:11 Reserved Read Only 0000 10:0 Scrambler Initializa- Read/Write Reset value is tion Key CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 13 ...
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Receive Error Count Register - Address 15h BIT NAME TYPE 15:0 Receive Error Read Only 0000h Counter CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Receive Error Counter Receive Error Counter ...
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Descrambler Key Initialization Register - Address 16h 15 14 Load 7 6 BIT NAME TYPE 15 Load Read/Set 14:11 Reserved Read Only 0000 10:0 Descrambler Initial- Read/Write Reset value is ization Key CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 13 ...
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PCS Sub-Layer Configuration Register - Address 17h 15 14 Time-Out Time-Out NRZI Enable Select Disable 7 6 CLK25 Disable Enable LT/100 CIM Disable BIT NAME TYPE 15 NRZI Enable Read/Write 1 14 Time-Out Select Read/Write 0 13 Time-Out Disable ...
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BIT NAME TYPE 9 MF Preamble Read/Write 0 Enable 8 Fast Test Read/Write 0 7 CLK25 Disable Read/Write When TCM pin is 6 Enable LT/100 Read/Write 1 5 CIM Disable Read/Write Reset to the logic 4 Tx Disable Read/Write 0 ...
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BIT NAME TYPE 3 Rx Disable Read/Write 0 2 LED1 Mode Read/Write 0 1 LED4 Mode Read/Write 0 0 Digital Reset Read/Write 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET DESCRIPTION When set, the receiver is disabled and no incoming ...
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Loopback, Bypass, and Receiver Error Mask Register - Address 18h 15 14 Bad SSD Bypass Bypass 4B5B Enable Scrambler 7 6 Loopback Alternate FDX Strip Preamble Transmit CRS Disable BIT NAME TYPE 15 Bad SSD Enable Read/Write 1 14 ...
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BIT NAME TYPE 8 PMD Loopback Read/Write 0 7 Strip Preamble Read/Write 0 6 Alternate FDX CRS Read/Write 0 5 Loopback Transmit Read/Write 1 Disable 4 Code Error Report Read/Write 0 Select 3 Premature End Read/Write 0 Error Report Select ...
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BIT NAME TYPE 2 Link Error Report Read/Write 0 Enable 1 Packet Error Report Read/Write 0 Enable 0 Code Error Report Read/Write 0 Enable CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET DESCRIPTION When set, this bit causes link errors to ...
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Self Status Register - Address 19h 15 14 Power Receiving Link OK Down 7 6 10BASE-T Full Duplex CIM Status Mode BIT NAME TYPE 15 Link OK Read Only 0 14 Power Down Read Only 1 13 Receiving Data ...
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BIT NAME TYPE 5 CIM Status Read Only 0 4:0 PHY Address Field Read/Write Reset to the val- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET When clear, this bit indicates that a stable link con- nection has been detected. When ...
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Status Register - Address 1Bh 15 14 Reserved 7 6 BIT NAME TYPE 15:11 Reserved Read Only 0 0000 10 Polarity OK Read Only 0 9 10BASE-T Serial Read/Write Reset to the value 8:0 Reserved Read Only 0 ...
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Configuration Register - Address 1Ch National LED3 Blink Compatibility Enable LT/10 Enable Mode BIT NAME TYPE 15:8 Reserved Read Only 0000 0000 7 National Compati- Read/Write 1 bility Mode 6 LED3 Blink Enable Read/Write ...
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BIT NAME TYPE 0 Jabber Enable Read/Write 1 7. DESIGN CONSIDERATIONS The CS8952 is a mixed-signal device containing the high-speed digital and analog circuits required to implement Fast Ethernet communication important the designer adhere to the following guidelines ...
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CS8952 68 Ω 8 SIGNAL- 9 SIGNAL+ 191 Ω 4 TX_NRZ- 5 TX_NRZ+ 82 Ω 6 RX_NRZ- 7 RX_NRZ+ 130 Ω Figure 7. Recommended Connection of Fiber Port TX_NRZ+/- termination components should be placed as close to the fiber transceiver ...
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CS8952 87 VSS 4.99 k Ω 86 RES 85 VSS Figure 8. Biasing Resistor Connection and Layout plied through the XTAL_I pin, or using an external clock source supplied through the TX_CLK pin. When a 25 MHz crystal is used, ...
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General Layout Recommendations The following PCB layout recommendations will help ensure reliable operation of the CS8952 and good EMC performance. • Use a multilayer Printed Circuit Board with at least one ground and one power plane. A typi- cal ...
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TX+/- traces. CS8952 Pin T1 Primary Pin Assignment Assignment 91 (RX+) 92 (RX-) 81 (TX-) 80 (TX+) • No signal current carrying planes, i.e. no ground or power plane, should be present un- derneath ...
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PIN DESCRIPTIONS Pin Diagram VSS 1 VDD 2 VSS 3 TX_NRZ- 4 TX_NRZ+ 5 RX_NRZ- 6 RX_NRZ+ 7 SIGNAL- 8 SIGNAL+ 9 VSS 10 VDD 11 VSS 12 VSS 13 RX_EN 14 RESET 15 REPEATER 16 CLK25 17 VSS ...
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MII Interface Pins COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48. Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex operation, COL is undefined and should be ignored. When configured for 10 Mb/s ...
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In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_CLK pin should have an external 33 Ω series resistor. For systems not required to ...
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RX_ER/PHYAD4/RXD4 - Receive Error/PHY Address 4/Receive Data 4. Input/Tri-State Output, Pin 37. During normal MII operation, this pin is defined as RX_ER (Receive Error). When RX_DV is high, RX_ER asserted high indicates that an error has been detected in the ...
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When the TCM pin is high on power-up or reset, the CLK25 pin may be used as a source for the TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally. TX_CLK should ...
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AN1 pin AN0 pin Auto-Negotiation may also be enabled and the advertised capabilities modified under software control through bit 8 of the Basic Mode ...
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BP4B5B - Bypass 4B5B Coders. Input, Pin 56. When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders ...
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ISODEF - Isolate Default. Input, Pin 63. When asserted high during power-up or reset, the MII will power-up electrically isolated except for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to the MII. ...
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LPSTRT - Low Power Start. Input, Pin 50. When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media ...
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REPEATER - REPEATER Mode Select. Input, Pin 16. This pin controls the operation of the CRS (Carrier Sense) pin as shown below: REPEATER pin high low low At power- reset, the value on this pin is latched into ...
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TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60. These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output waveform. The rise and fall times are symmetric. TXSLEW0 pin low low low ...
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RESET - Reset. Input, Pin 15. This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3. XTAL_I - ...
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PACKAGE DIMENSIONS 100L TQFP PACKAGE DRAWING D D1 ∝ L DIM ∝ * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 CrystalLAN™ 100BASE-X and 10BASE-T ...
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ORDERING INFORMATION Part # CS8952-CQZ CS8952-IQZ 11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS8952-CQZ CS8952-IQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Temperature Range 0 °C to +70 °C ...
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... OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, CrystalLAN, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. ...