LXT384BE Intel Corporation, LXT384BE Datasheet
LXT384BE
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LXT384BE Summary of contents
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LXT384 Octal T1/E1/J1 Line Interface Unit The LXT384 is an octal short haul Pulse Code Modulation (PCM) Line Interface Unit for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates eight independent receivers and eight independent ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ® ...
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Contents 1.0 Pin Assignments and Signal Descriptions.......................................................................... 9 2.0 Functional Description......................................................................................................22 2.1 Initialization..........................................................................................................22 2.1.1 Reset Operation .....................................................................................23 2.2 Receiver ..............................................................................................................23 2.2.1 Loss of Signal Detector ..........................................................................23 2.2.1.1 E1 Mode ....................................................................................24 2.2.1.2 T1 Mode ....................................................................................24 2.2.1.3 Data Recovery Mode.................................................................24 2.2.2 Alarm ...
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LXT384 — Octal T1/E1/J1 Line Interface Unit 4.3 TAP Controller..................................................................................................... 46 4.4 JTAG Register Description.................................................................................. 48 4.4.1 Boundary Scan Register (BSR).............................................................. 49 4.4.2 Analog Port Scan Register (ASR) .......................................................... 52 4.4.3 Device Identification Register (IDR) ....................................................... 53 4.4.4 Bypass Register ...
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Low Quad Flat Packages (LQFP) Dimensions....................................................78 37 Plastic Ball Grid Array (PBGA) Package Dimensions .........................................79 Tables 1 LXT384 Pin Description.......................................................................................11 2 Line Length Equalizer Inputs...............................................................................27 3 Jitter Attenuation Specifications ..........................................................................30 4 Operation Mode Summary ..................................................................................34 5 Microprocessor Interface Selection ...
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LXT384 — Octal T1/E1/J1 Line Interface Unit 46 JTAG Timing Characteristics .............................................................................. 62 47 Intel Mode Read Timing Characteristics2 ........................................................... 63 48 Intel Mode Write Timing Characteristics2 ........................................................... 65 49 Motorola Bus Read Timing Characteristics2....................................................... 67 50 Motorola Mode Write ...
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Applications SONET/SDH tributary interfaces Digital cross connects Public/private switching trunk line interfaces Figure 1. LXT384 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP RRING TTIP TRING Datasheet Octal T1/E1/J1 Transceiver — LXT384 Microwave transmission systems M13, E1-E3 MUX HARDWARE / ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 2. LXT384 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP7 RRING7 TTIP7 TRING7 RTIP6/RRING6 TTIP6/TRING6 RTIP5/RRING5 TTIP5/TRING5 RTIP4/RRING4 TTIP4/TRING4 RTIP3/RRING3 TTIP3/TRING3 RTIP2/RRING2 TTIP2/TRING2 RTIP1/RRING1 TTIP1/TRING1 Transceiver 0 RTIP0 RRING0 MUX TTIP0 TRING0 A3 - ...
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Pin Assignments and Signal Descriptions Figure 3. LXT384 Low-Profile Quad Flate Package (LQFP) 144-Pin Assignments and Package Markings TPOS7/TDATA7 1 TCLK7 2 LOS6 3 RNEG6/BPV6 4 5 RPOS6/RDATA6 RCLK6 6 TNEG6/UBS6 7 TPOS6/TDATA6 8 TCLK6 9 MCLK 10 MODE ...
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... TGND RRING RRING TRING TGND RTIP RTIP TGND TTIP TGND RRING RRING TGND LXT384BE (BOTTOM VIEW) TTIP TGND TGND RRING RRING TRING TGND RTIP RTIP TGND TTIP TGND TGND RRING RRING 3 ...
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Table 1. LXT384 Pin Description (Sheet 1 of 12) Pin # Ball # Symbol QFP PBGA 1 B2 TPOS7 1 B2 TDATA7 2 B1 TCLK7 3 E3 LOS6 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 2 of 12) Pin # Ball # Symbol QFP PBGA 4 C3 RNEG6 C3 BPV6 RPOS6 5 C2 RDATA6 6 C1 RCLK6 1. DI: Digital Input; ...
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Table 1. LXT384 Pin Description (Sheet 3 of 12) Pin # Ball # Symbol QFP PBGA 7 D3 TNEG6 7 D3 UBS6 8 D2 TPOS6 8 D2 TDATA6 9 D1 TCLK6 10 E1 MCLK 1. DI: Digital Input; DO: Digital ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 4 of 12) Pin # Ball # Symbol QFP PBGA 11 E2 MODE DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; ...
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Table 1. LXT384 Pin Description (Sheet 5 of 12) Pin # Ball # Symbol QFP PBGA VCCIO0 18 G4 GNDIO0 19 H1 VCC0 20 H4 GND0 1. DI: Digital Input; ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 6 of 12) Pin # Ball # Symbol QFP PBGA 21 G2 LOOP0/ LOOP1/ LOOP2/ LOOP3/ LOOP4/ LOOP5/D5 27 ...
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Table 1. LXT384 Pin Description (Sheet 7 of 12) Pin # Ball # Symbol QFP PBGA 43 K2 MUX 44 N4, P4 TVCC0 45 N5 TTIP0 46 P5 TRING0 47 N6, P6 TGND0 48 P7 RTIP0 49 N7 RRING0 50 ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 8 of 12) Pin # Ball # Symbol QFP PBGA 69 P12 RNEG3 69 P12 BPV3 70 P13 RPOS3 70 P13 RDATA3 71 P14 RCLK3 72 N12 TNEG3 72 ...
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Table 1. LXT384 Pin Description (Sheet 9 of 12) Pin # Ball # Symbol QFP PBGA 84 J14 84 J14 84 J14 84 J14 LEN0 85 J13 85 J13 85 J13 LEN1 86 J12 86 J12 SCLK 86 J12 86 ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 10 of 12) Pin # Ball # Symbol QFP PBGA MOT/INTL/ 88 H12 CODEN 89 H11 GND1 90 H14 VCC1 91 G11 GNDIO1 92 G14 VCCIO1 93 G13 94 ...
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Table 1. LXT384 Pin Description (Sheet 11 of 12) Pin # Ball # Symbol QFP PBGA 108 B13 TPOS4 108 B13 TDATA4 109 B12 TNEG4 109 B12 UBS4 110 A14 RCLK4 111 A13 RPOS4 111 A13 RDATA4 112 A12 RNEG4 ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 12 of 12) Pin # Ball # Symbol QFP PBGA 129 D5 TTIP6 130 C5 TRING6 131 C6, D6 TGND6 132 C7 RTIP6 133 D7 RRING6 134 A6, B6 ...
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Reset Operation Writing to the reset register (RES) initiates a 1 microsecond reset cycle, except in Intel non- multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please refer to Host mode section for more information. ...
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LXT384 — Octal T1/E1/J1 Transceiver required for receive operation. When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the data content at the receiver ...
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The AIS condition is cleared when, within two consecutive 512 bit periods more zeros are detected for each 512 bit period. 2.2.2.2 T1 Mode ANSI T1.231 detection is employed. The AIS condition is declared when less than 9 ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 5. 50% AMI Encoding TTIP Bit Cell TRING Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse shaper is bypassed if no MCLK is supplied while TCLK ...
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Table 2. Line Length Equalizer Inputs LEN2 LEN1 LEN0 Line length from LXT384 to DSX-1 cross-connect point. 2. Maximum cable loss ...
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LXT384 — Octal T1/E1/J1 Transceiver charge window, a driver short circuit fail (DFM) is reported in the respective register by setting an interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. Note: ...
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Figure 6. External Transmit/Receive Line Circuitry TVCC 0.1 F 3.3V VCC 0.1 F GND LXT384 (ONE CHANNEL) 1 Common decoupling capacitor for all TVCC and TGND pins. 2 Typical value. Adjust for actual board parasitics to obtain ...
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LXT384 — Octal T1/E1/J1 Transceiver 2.5 Line Protection Figure 6 on page 29 series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (70 k typ.) the resistors do not affect the ...
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Figure 7. Jitter Attenuator Loop TPOS RPOSi TNEG RNEGi TCLK RCLKi JASEL0 MCLK 2.7 Loopbacks The LXT384 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software ...
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LXT384 — Octal T1/E1/J1 Transceiver 2.7.2 Digital Loopback The digital loopback function is available in software mode only. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS & ...
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Figure 11. TAOS Data Path MCLK TAOS mode TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Figure 12. TAOS with Digital Loopback MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Figure 13. TAOS with Analog Loopback MCLK ...
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LXT384 — Octal T1/E1/J1 Transceiver The monitored line signal (input or output) goes through channel 0 clock and data recovery. The signal can be observed digitally at the RCLK/RPOS/RNEG outputs. This feature can also be used to create timing interfaces ...
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Table 4. Operation Mode Summary (Continued) MCLK TCLK H Clocked Hardware mode only. 2.11 Interfacing with 5V Logic The LXT384 can interface directly with 5V TTL family devices. The ...
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LXT384 — Octal T1/E1/J1 Transceiver delay to allow the reset cycle to completely initialize the device before proceeding. The overall duration of the Reset cycle from CS low to Reset cycle completion is 3 microseconds when using Intel non-multiplexed host ...
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Interrupt Enable The LXT384 provides a latched interrupt output (INT). An interrupt occurs any time there is a transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM and AIS interrupt ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 14. Serial Host Mode Timing CS SCLK R/W SDI R Read from LXT384 R Write to LXT384 X = Don’t care 3.0 Register Descriptions Table 6. Serial and Parallel Port ...
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Table 6. Serial and Parallel Port Register Addresses (Sheet Digital Loopback LOS/AIS Criteria Selection Automatic TAOS Select Global Control Register Pulse Shaping Indirect Address Register Pulse Shaping Data Register Output Enable Register AIS Status Register AIS Interrupt ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 7. Register Bit Names (Sheet Register Name Global Control Register Pulse Shaping Indirect Address PSIAD R/W Register Pulse Shaping PSDAT R/W Data Register Output Enable Register AIS Status Register AIS Interrupt ...
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Table 12. LOS Status Monitor Register, LOS (04h) 1 Bit Name 7-0 LOS7-LOS0 1. On power up all register bits are set to “0”. Any change in the state causes an interrupt. All LOS interrupts are cleared by a single ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 18. Software Reset Register, RES (0Ah) Bit Name 7-0 RES7-RES0 Table 19. Performance Monitoring Register, MON (0Bh) Bit Name 3-0 A3:A0 4-7 reserved Table 20. Digital Loopback Register, DL (0Ch) 1 Bit Name 7-0 ...
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Table 23. Global Control Register, GCR (0Fh) 1 Bit Name 0 JASEL0 1 JASEL1 2 JACF 3 FIFO64 4 CODEN 5 CDIS 6 RAISEN power-on reset the register is set to “0”. Table 24. Pulse Shaping ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 25. Pulse Shaping Data Register, PSDAT (11h) Bit Name 1, 3 0-2 LEN 0 power-on reset the register is set to “0”. 2. Maximum cable loss at 772 ...
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Table 29. AIS Interrupt Status Register, AISIS (15h) 1 Bit Name 7-0 AISIS7-AISIS0 1. On power-up all the register bits are set to “0”. 4.0 JTAG Boundary Scan 4.1 Overview The LXT384 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 15. JTAG Architecture TDI TCK TMS Controller TRST 4.3 TAP Controller The TAP controller state synchronous state machine controlled by the TMS input and clocked by TCK (see an instruction, receiving ...
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Table 30. TAP State Description (Sheet State Update - IR Loads a new instruction into the instruction register. Pause - IR Momentarily pauses shifting of data through the data/instruction registers. Pause - DR Exit1 - IR Exit1 ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 4.4 JTAG Register Description The following paragraphs describe each of the registers represented SELECT- CAPTURE- ...
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Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 31. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 N/A 31 RNEG0 32 LOS0 33 MUX 34 ...
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Table 31. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 57 MOT/INTL 58 TCLK5 59 TPOS5 60 TNEG5 61 RCLK5 62 RPOS5 63 N/A 64 RNEG5 65 LOS5 66 TCLK4 67 TPOS4 68 TNEG4 ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 31. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 89 TNEG6 90 TPOS6 91 TCLK6 92 MCLK 93 MODE ...
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Figure 17. Analog Test Port Application 4.4.3 Device Identification Register (IDR) The IDR register provides access to the manufacturer number, part number and the LXT384 revision. The register is arranged per IEEE 1149.1 and is represented in is shifted in ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 34. Instruction Register (IR) Instruction EXTEST INTEST_ANALOG SAMPLE / PRELOAD IDCODE BYPASS 5.0 Test Specifications Note: Table 35 through Table 54 specifications of the LXT384 and are guaranteed by test except, where noted, by ...
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Table 36. Recommended Operating Conditions Parameter Digital supply voltage (VCC and VCCIO) Transmitter supply voltage, TVCC=5V nominal Transmitter supply voltage, TVCC=3.3V nominal Ambient operating temperature Average transmitter power supply current Mode Average digital power 1, 3 supply ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 37. DC Characteristics (Sheet Parameter Low level input voltage Midrange level input voltage MODE, LOOP0-7 High level input and voltage JASEL Low level input current High level input current Input leakage ...
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Table 38. E1 Transmit Transmission Characteristics (Sheet Parameter Transmit intrinsic jitter; 20Hz to 100kHz Transmit path delay 1. Guaranteed by design and other correlation methods. Table 39. E1 Receive Transmission Characteristics Parameter Permissible cable attenuation Receiver dynamic ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 40. T1 Transmit Transmission Characteristics Parameter Output pulse amplitude Peak voltage of a space Driver output impedance Transmit amplitude variation with power supply Ratio of positive to negative pulse amplitude Difference between pulse sequences ...
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Table 41. T1 Receive Transmission Characteristics (Sheet Parameter Low limit 0.1Hz to 1Hz input jitter 4.9Hz to 300Hz 1 tolerance 10KHz to 100KHz Differential receiver input impedance Input termination resistor tolerance Common mode input impedance to ground ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 42. Jitter Attenuator Characteristics (Sheet Parameter Input jitter tolerance before FIFO overflow or underflow E1 jitter attenuation T1 jitter attenuation Output Jitter in remote loopback 1. Guaranteed by design and other ...
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Table 44. Transmit Timing Characteristics (Sheet Parameter TCLK to TPOS/TNEG hold time Delay time OE Low to driver High Z Delay time TCLK Low to driver High Z Figure 18. Transmit Clock Timing Diagram TCLK TPOS TNEG ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 45. Receive Timing Characteristics (Sheet Parameter RCLK Rising to RPOS/RNEG hold time Delay time between RPOS/RNEG and RCLK 1. RCLK duty cycle widths will vary depending on extent of received pulse ...
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Figure 20. JTAG Timing TCK TMS TDI TDO Table 47. Intel Mode Read Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch active to active read setup time Chip select setup time to active read ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 21. Non-Multiplexed Intel Mode Read Timing ALE (pulled High INT tDRDY Tristate RDY Figure 22. Multiplexed Intel Mode Read Timing tVL ALE CS RD tSALR ADDRESS ...
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Table 48. Intel Mode Write Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch active to active write setup time Chip select setup time to active write Chip select hold time from inactive write Address ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 23. Non-Multiplexed Intel Mode Write Timing A4-A0 (pulled High) ALE CS WR D7-D0 INT tDRDY Tristate RDY Figure 24. Multiplexed Intel Mode Write Timing ALE tVL CS WR tSALW AD7-AD0 ADDRESS INT Tristate RDY ...
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Table 49. Motorola Bus Read Timing Characteristics Address setup time to address or data strobe Address hold time from address or data strobe Valid address strobe pulse width R/W setup time to active data strobe R/W hold time from inactive ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 25. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS (pulled High) tSRW R D7-D0 INT ACK Figure 26. Multiplexed Motorola Mode Read Timing AS tSRW R/W CS tASDS DS tSAR D7-D0 ...
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Table 50. Motorola Mode Write Timing Characteristics Address setup time to address strobe Address hold time to address strobe Valid address strobe pulse width R/W setup time to active data strobe R/W hold time from inactive data strobe Chip select ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 28. Multiplexed Motorola Mode Write Timing AS R D7-D0 INT ACK Table 51. Serial I/O Timing Characteristics Parameter Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time ...
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Figure 29. Serial Input Timing SCLK t DC LSB SDI CONTROL BYTE Figure 30. Serial Output Timing CLKE = SCLK CS SDO CLKE = SCLK ...
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LXT384 — Octal T1/E1/J1 Transceiver Table 53. G.703 2.048 Mbit/s Pulse Mask Specifications Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of ...
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Figure 32. T1, T1.102 Mask Templates -0.80 -0.60 -0.40 Datasheet Octal T1/E1/J1 Transceiver — LXT384 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 0.00 0.20 0.40 -0.20 -0.40 -0.60 Tim e [UI] 0.60 0.80 1.00 1.20 73 ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 33. LXT384 Jitter Tolerance Performance 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 ...
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Figure 34. LXT384 Jitter Transfer Performance 0 3Hz 0 dB -10 dB -20 dB -30 dB -40 dB - ...
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LXT384 — Octal T1/E1/J1 Transceiver Figure 35. LXT384 Output Jitter for CTR12/13 Applications 0.2 0.15 0.1 0. 100 Hz 5.1 Recommendations and Specifications • AT&T Pub 62411 • ANSI T1.102 - 199X Digital Hierarchy Electrical ...
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G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy • O.151 Specification of instruments to measure error performance in digital systems • OFTEL OTR-001 Short Circuit Current Requirements Datasheet Octal ...
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LXT384 — Octal T1/E1/J1 Transceiver 6.0 Mechanical Specifications Figure 36. Low Quad Flat Packages (LQFP) Dimensions 144 Pin LQFP • Part Number LXT384LE • Extended Temperature Range (- D/2 E1 Dimension ...
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... Figure 37. Plastic Ball Grid Array (PBGA) Package Dimensions 160 Pin PBGA • • 15.00 13.00 ±0.20 4.72 ±0.10 PIN #A1 CORNER PIN #A1 ID 4.72 ±0.10 Ø1.00 (3 plcs) TOP VIEW SIDE VIEW Datasheet Octal T1/E1/J1 Transceiver — LXT384 Part Number LXT384BE Extended Temperature Range (- 1.00 REF A B 0.50 ±0. 13.00 15.00 ±0. ...
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