MC68HC11E1FU Motorola, MC68HC11E1FU Datasheet
MC68HC11E1FU
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MC68HC11E1FU Summary of contents
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... M68HC11 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS M68HC11E Family Data Sheet M68HC11E/D Rev. 5 6/2003 ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. M68HC11E Family — Rev. 5 MOTOROLA © ...
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... Revision History Page Number(s) 49 191 191 — SCCR1 bit 4 (M) 123 — Title changed to 169 — Title 170 173 — Title changed to include 179 — 183 — Title 185 — Title 188 191 197 Throughout 26 191 M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 EB296 — Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . . 263 M68HC11E Family — Rev. 5 MOTOROLA and Mechanical Specifications . . . . . . . . . . . . . . . . . . . 193 List of Sections List of Sections Data Sheet 5 ...
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... List of Sections Data Sheet 6 List of Sections M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal Driver and External Clock Input (XTAL and EXTAL E-Clock Output ( Interrupt Request (IRQ Non-Maskable Interrupt (XIRQ/V MODA and MODB (MODA/LIR and MODB/V ...
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... CONFIG Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 3. Analog-to-Digital (A/D) Converter Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 A/D Converter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Section 4. Central Processor Unit (CPU) Accumulators A, B, and Index Register X (IX Index Register Y (IY Table of Contents M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA Stack Pointer (SP Program Counter (PC Condition Code Register (CCR Carry/Borrow ( Overflow ( Zero ( Negative ( Interrupt Mask (I Half Carry ( Interrupt Mask ( STOP Disable ( Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Immediate ...
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... Section 7. Serial Communications Interface (SCI) Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Address-Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Serial Communications Data Register . . . . . . . . . . . . . . . . . . . . . . 122 Serial Communications Control Register 123 Serial Communications Control Register 124 Serial Communication Status Register . . . . . . . . . . . . . . . . . . . . . . 125 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table of Contents M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA Section 8. Serial Peripheral Interface (SPI) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Master Out/Slave 136 Serial Clock 136 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SPI System Errors ...
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... Thin Quad Flat Pack (Case 848D 201 Data Sheet 12 Section 10. Electrical Characteristics and Extended Voltage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Section 11. Ordering Information and Mechanical Specifications (3.0 Vdc to 5.5 Vdc 197 (Case 778B 199 Table of Contents M68HC11E Family — Rev. 5 MOTOROLA ...
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... MOTOROLA 56-Pin Dual in-Line Package (Case 859 202 Appendix A. Development Support Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Motorola M68HC11 E-Series Development Tools . . . . . . . . . . . . . . . . 203 EVS — Evaluation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Motorola Modular Development System (MMDS11 204 SPGMR11 — Serial Programmer for M68HC11 MCUs . . . . . . . . . . . . 206 Appendix B. EVBU Schematic ...
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... Table of Contents Data Sheet 14 Table of Contents M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA Random-access memory (RAM) Read-only memory (ROM) Erasable programmable read-only memory (EPROM) Electrically erasable programmable read-only memory (EEPROM) Several low-voltage devices are also available. M68HC11 CPU Power-saving stop and wait modes Low-voltage devices available (3.0– ...
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... MC68HC811E2 only 56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP) for a functional diagram of the E-series MCUs. Differences among General Description Figure 1-1. M68HC11E Family — Rev. 5 MOTOROLA ...
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... CLOCK LOGIC TIMER SYSTEM BUS EXPANSION ADDRESS PORT A PORT applies only to devices with EPROM/OTPROM. PPE Figure 1-1. M68HC11 E-Series Block Diagram M68HC11E Family — Rev. 5 MOTOROLA IRQ XIRQ/V RESET PPE* INTERRUPT LOGIC M68HC11 CPU ADDRESS/DATA STROBE AND HANDSHAKE PARALLEL I/O CONTROL PORT C ...
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... EPROM/OTPROM. PPE Figure 1-2. Pin Assignments for 52-Pin PLCC and CLCC General Description Figure 1-3, Figure 1-4, Figure 1-5, and 46 PE5/AN5 PE1/AN1 45 44 PE4/AN4 43 PE0/AN0 42 PB0/ADDR8 PB1/ADDR9 41 40 PB2/ADDR10 PB3/ADDR11 39 PB4/ADDR12 38 37 PB5/ADDR13 36 PB6/ADDR14 PB7/ADDR15 35 34 PA0/IC3 M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA 1 PA0/IC3 PB7/ADDR15 5 PB6/ADDR14 6 PB5/ADDR13 7 PB4/ADDR12 8 M68HC11 E SERIES PB3/ADDR11 9 PB2/ADDR10 10 11 PB1/ADDR9 12 PB0/ADDR8 PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 applies only to devices with EPROM/OTPROM. PPE Figure 1-3. Pin Assignments for 64-Pin QFP General Description General Description ...
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... PE4/AN4 12 PE1/AN1 PE5/AN5 applies only to devices with EPROM/OTPROM. PPE Figure 1-4. Pin Assignments for 52-Pin TQFP General Description PD0/RxD 39 IRQ 38 (1) XIRQ/V 37 PPE 36 RESET 35 PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 34 PC5/ADDR5/DATA5 33 32 PC4/ADDR4/DATA4 31 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 30 PC1/ADDR1/DATA1 29 28 PC0/ADDR0/DATA0 27 XTAL M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL 8 PC0/ADDR0/DATA0 9 PC1/ADDR1/DATA1 10 PC2/ADDR2/DATA2 11 PC3/ADDR3/DATA3 12 PC4/ADDR4/DATA4 13 PC5/ADDR5/DATA5 14 PC6/ADDR6/DATA6 M68HC11 E SERIES 15 PC7/ADDR7/DATA7 16 RESET 17 * XIRQ/V PPE 18 IRQ 19 PD0/RxD PD1/TxD 22 PD2/MISO 23 PD3/MOSI 24 PD4/SCK 25 PD5/ applies only to devices with EPROM/OTPROM. ...
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... MODB/V 24 STBY General Description PD5/ PD4/SCK PD3/MOSI 45 44 PD2/MISO PD1/TxD 43 42 PD0/RxD IRQ 41 40 XIRQ RESET 39 38 PC7/ADDR7/DATA7 37 PC6/ADDR6/DATA6 36 PC5/ADDR5/DATA5 35 PC4/ADDR4/DATA4 34 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 33 PC1/ADDR1/DATA1 32 PC0/ADDR0/DATA0 31 30 XTAL 29 EXTAL 28 STRB/R STRA/AS 25 MODA/LIR M68HC11E Family — Rev. 5 MOTOROLA ...
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... MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. MANUAL RESET SWITCH OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH M68HC11E Family — Rev. 5 MOTOROLA and 4.7 kΩ ...
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... The Seiko S0854HN (or other S805 series devices): a. Extremely low power (2 µA) a. TO-92 package a. Limited temperature range, –20°C to +70°C a. Available in various trip-point voltage ranges 2. The Motorola MC34064: a. TO-92 or SO-8 package a. Draws about 300 µA a. Temperature range –40°C to 85°C a. Well controlled trip point a ...
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... MCU. Either negative edge-sensitive triggering or level-sensitive triggering is program selectable (OPTION register). IRQ is always configured to level-sensitive triggering at reset. When using IRQ in a level-sensitive wired-OR configuration, connect an external pullup resistor, typically 4.7 kΩ M68HC11E Family — Rev. 5 MOTOROLA EXTAL 10 MΩ MCU XTAL Figure 1-9 ...
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... For more information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set Errata 3 (Motorola document order number 68HC711E9MSE3. 1.4.7 MODA and MODB (MODA/LIR and MODB/V During reset, MODA and MODB select one of the four operating modes: • ...
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... R high-impedance state. Refer to Memory M68HC11E Family — Rev. 5 MOTOROLA pin is used to input random-access memory (RAM) standby power. voltage, the internal RAM and part of the reset logic are powered DD input. This allows RAM contents to be retained DD power applied to the MCU ...
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... It drives the pins only if they are configured as outputs. Writes to PORTA do not change the pin state when pins are configured for timer input captures or output compares. Refer to Data Sheet 28 for a functional description of the 40 port signals within different Section 6. Parallel Input/Output (I/O) General Description Ports. M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11E Family — Rev. 5 MOTOROLA Table 1-1. Port Signal Functions Single-Chip and Port/Bit Bootstrap Modes PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB0 PB1 PB1 PB2 PB2 PB3 PB3 PB4 PB4 PB5 PB5 PB6 PB6 PB7 PB7 PC0 PC0 PC1 ...
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... It is customary to have an external pullup resistor on lines that are driven by open-drain devices. Port C can only be configured for wired-OR operation when the MCU is in single-chip mode. Refer to Ports for additional information about port C functions. Data Sheet 30 Section 6. Parallel Input/Output (I/O) General Description M68HC11E Family — Rev. 5 MOTOROLA ...
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... If high accuracy is required for A/D conversions, avoid reading port E during sampling, as small disturbances can reduce the accuracy of that result. M68HC11E Family — Rev. 5 MOTOROLA PD2 is the master in/slave out (MISO) signal. PD3 is the master out/slave in (MOSI) signal. PD4 is the serial clock (SCK) signal. ...
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... General Description Data Sheet 32 General Description M68HC11E Family — Rev. 5 MOTOROLA ...
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... In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes: • • M68HC11E Family — Rev. 5 MOTOROLA Section 2. Operating Modes and On-Chip Memory In single-chip mode only on-chip memory is available. Expanded mode, however, allows access to external memory. Bootstrap, a variation of the single-chip mode special mode that executes a bootloader program in an internal bootstrap ROM ...
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... Figure NOTE: The write enable signal for an external memory is the NAND of the E clock and the inverted R/W signal. 2.2.3 Test Mode Test mode, a variation of the expanded mode, is primarily used during Motorola’s internal production testing; however accessible for programming the Data Sheet 34 2-1. ...
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... INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be inaccessible. Refer to Reset states shown are for single-chip mode only. M68HC11E Family — Rev. 5 MOTOROLA Figure 2-6. Mode, that is included in this data book. 2-5, and Figure ...
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... EXT B600 512 BYTES EEPROM B7FF BOOT BF00 EXT ROM BFFF FFC0 NORMAL MODES INTERRUPT FFFF VECTORS SPECIAL TEST Operating Modes and On-Chip Memory BFC0 SPECIAL MODES INTERRUPT VECTORS BFFF BFC0 SPECIAL MODES INTERRUPT VECTORS BFFF M68HC11E Family — Rev. 5 MOTOROLA ...
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... EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP * 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. Figure 2-5. Memory Map for MC68HC(7)11E20 M68HC11E Family — Rev. 5 MOTOROLA EXT EXT EXT BOOTSTRAP SPECIAL TEST EXT EXT EXT EXT BOOTSTRAP ...
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... FFFF FFFF VECTORS PA4 PA3 PA2 PA1 OIN PLS EGA PC4 PC3 PC2 PC1 PB4 PB3 PB2 PB1 Reserved U = Unaffected M68HC11E Family — Rev. 5 MOTOROLA Bit 0 PA0 I R INVB 1 PC0 PB0 0 ...
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... Timer Input Capture 1 Register $1010 High (TIC1H) See page 147. Timer Input Capture 1 Register $1011 Low (TIC1L) See page 147. Figure 2-7. Register and Control Bit Assignments (Sheet M68HC11E Family — Rev. 5 MOTOROLA Bit Read: PCL7 PCL6 PCL5 Write: Reset: ...
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... Bit Bit 11 Bit 10 Bit Bit 3 Bit 2 Bit Reserved U = Unaffected M68HC11E Family — Rev. 5 MOTOROLA Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 ...
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... See page 162. Serial Peripheral Control Register $1028 (SPCR) See page 138. Serial Peripheral Status Register $1029 (SPSR) See page 139. Figure 2-7. Register and Control Bit Assignments (Sheet M68HC11E Family — Rev. 5 MOTOROLA Bit Read: Bit 15 Bit 14 Bit 13 Write: Reset: 1 ...
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... R3/T3 R2/T2 R1/ Indeterminate after reset Bit 3 Bit 2 Bit 1 Bit 3 Bit 2 Bit 1 Bit 3 Bit 2 Bit 1 Bit 3 Bit 2 Bit 1 BPRT3 BPRT2 BPRT1 Reserved U = Unaffected M68HC11E Family — Rev. 5 MOTOROLA Bit 0 Bit 0 SCR0 U 0 SBK 0 0 R0/T0 CA Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 1 ...
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... See page 48. 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. 2. MC68HC711E9 only 3. MC68HC811E2 only Figure 2-7. Register and Control Bit Assignments (Sheet M68HC11E Family — Rev. 5 MOTOROLA Bit Read: MBE ELAT ...
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... DD V OUT V BATT 4.8-V NiCd + Figure 2-8. RAM Standby MODB/V Operating Modes and On-Chip Memory powers DD pin can supply RAM power from a Figure 2-8 shows a typical . STBY DD Section 5. Resets and Interrupts. 4 MODB/V STBY OF M68HC11 Connections STBY M68HC11E Family — Rev. 5 MOTOROLA is is ...
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... Refer to bits, and the four operating modes. MODB M68HC11E Family — Rev. 5 MOTOROLA ), which allows RAM contents to be maintained in absence of STBY Table 2-1, which is a summary of mode pin operation, the mode control Table 2-1. Hardware Mode Select Summary Input Levels at Reset ...
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... Bootstrap 0 1 Special test Operating Modes and On-Chip Memory Section 5. Resets and Interrupts (1) PSEL3 PSEL2 PSEL1 PSEL0 Latched at Reset SMOD MDA M68HC11E Family — Rev. 5 MOTOROLA Bit ...
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... Timer interrupt mask 2 (TMSK2) $x035 Block protect register (BPROT) $x039 System configuration options (OPTION) Highest priority I-bit interrupt and $x03C miscellaneous (HPRIO) $x03D RAM and I/O map register (INIT) M68HC11E Family — Rev. 5 MOTOROLA IRVNE Out E Clock Out Mode of Reset of Reset ...
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... Bulk erase • Byte programming • Communication server All of this functionality is provided by PCbug11 which can be found on the Motorola Web site at http://www.motorola.com/semiconductors/. For more information on using PCbug11 to program an E-series device, Motorola engineering bulletin EB296 entitled M68HC11EVBU NOTE: The CONFIG register on the 68HC11 is an EEPROM cell and must be programmed accordingly ...
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... COP is controlled by the DISR bit in TEST1 register. Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG) EE[3:0] — EEPROM Mapping Bits EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any 4-Kbyte boundary. See M68HC11E Family — Rev. 5 MOTOROLA $103F Bit ...
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... Refer to Data Sheet 50 Section 5. Resets and Interrupts. Bit RAM3 RAM2 RAM1 RAM0 Figure 2-12. RAM and I/O Mapping Register (INIT) Table 2-4. Operating Modes and On-Chip Memory Bit 0 REG3 REG2 REG1 REG0 M68HC11E Family — Rev. 5 MOTOROLA ...
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... Address: $1039 Read: Write: Reset: 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. M68HC11E Family — Rev. 5 MOTOROLA Table Table 2-4. RAM Mapping RAM[3:0] Address 0000 $0000–$0xFF 0001 $1000– ...
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... MCU resumes processing within about four bus cycles. started up from the stop power-saving mode. This delay allows the crystal oscillator to stabilize. Section 5. Resets and Interrupts. 15 before it enters the COP watchdog system. Interrupts. Operating Modes and On-Chip Memory Converter. for more information M68HC11E Family — Rev. 5 MOTOROLA ...
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... Any operating mode can be used. This example applies to all devices with EPROM/OTPROM except for the MC68HC711E20. EPROG This example applies only to MC68HC711E20. EPROG M68HC11E Family — Rev. 5 MOTOROLA ). Normal programming is accomplished using PPE LDAB #$20 STAB $103B Set ELAT bit in (EPGM = 0) to enable EPROM latches ...
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... After the last byte to be programmed is sent and the corresponding verification data is returned, the programming operation is terminated by resetting the MCU. For more information, Motorola application note AN1060 entitled Bootstrap Mode 2.4.3 EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register (PPROG) enables the EPROM programming voltage and controls the latching of data to be programmed. • ...
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... MBE can be written only in special modes EPROM array configured for normal programming 1 = Program two bytes with the same data M68HC11E Family — Rev. 5 MOTOROLA a. EPGM enables the high voltage necessary for both EEPROM and EPROM/OTPROM programming. b. ELAT and EELAT are mutually exclusive and cannot both equal 1. ...
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... EXROW can be read and written only in special modes and always returns 0 in normal modes Function Selected Operating Modes and On-Chip Memory Normal mode Reserved Gate stress Drain stress M68HC11E Family — Rev. 5 MOTOROLA ...
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... EEPROM and the CONFIG register. In test or bootstrap modes, write protection is inhibited and BPROT can be written repeatedly. Address ranges for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to Figure M68HC11E Family — Rev. 5 MOTOROLA 2-16. Operating Modes and On-Chip Memory Operating Modes and On-Chip Memory EEPROM ...
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... BPRT3 $xE00–$xFFF Operating Modes and On-Chip Memory Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 Block Size 32 bytes 64 bytes 128 bytes 288 bytes Block Size (1) 512 bytes (1) 512 bytes (1) 512 bytes (1) 512 bytes Figure 2-13. M68HC11E Family — Rev. 5 MOTOROLA ...
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... Normal read or program mode 1 = Erase mode EELAT — EEPROM Latch Control Bit 0 = EEPROM address and data bus configured for normal reads and cannot 1 = EEPROM address and data bus configured for programming or erasing M68HC11E Family — Rev. 5 MOTOROLA Bit (1) ODD ...
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... STAB 0,X Write any data to any address in ROW LDAB #$0F ROW = 1, ERASE = 1, EELAT = 1, EPGM = 1 STAB $103B Turn on high voltage JSR DLY10 Delay 10 ms CLR $103B Turn off high voltage and set to READ mode Operating Modes and On-Chip Memory M68HC11E Family — Rev. 5 MOTOROLA ...
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... An enhanced security feature which protects EPROM contents, RAM, and EEPROM from unauthorized accesses is available in MC68S711E9. Refer to Section 11. Ordering Information and Mechanical Specifications part number. M68HC11E Family — Rev. 5 MOTOROLA LDAB #$16 BYTE = 1, ERASE = 1, EELAT = 1 STAB $103B Set to BYTE erase mode ...
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... EB183 — with PCbug11 on the M68HC711E9PGMR • EB188 — PCbug11 on the M68HC711E9PGMR Data Sheet 62 Enabling the Security Feature on the MC68HC711E9 Devices Enabling the Security Feature on M68HC811E2 Devices with Operating Modes and On-Chip Memory M68HC11E Family — Rev. 5 MOTOROLA ...
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... V do not cause a latchup problem, although current should be limited according DD to maximum ratings. Refer to input pin. M68HC11E Family — Rev. 5 MOTOROLA Section 3. Analog-to-Digital (A/D) Converter Figure 3-2, which is a functional diagram of an Analog-to-Digital (A/D) Converter Figure 3-1. ...
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... ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR2 A/D RESULT 2 ADR3 A/D RESULT 3 DIFFUSION/POLY COUPLER + ~12V ð 4 kΩ – ~0.7V 400 nA JUNCTION DUMMY N-CHANNEL LEAKAGE OUTPUT DEVICE Analog-to-Digital (A/D) Converter INTERNAL DATA BUS ADR4 A/D RESULT DAC CAPACITANCE V RL M68HC11E Family — Rev. 5 MOTOROLA ...
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... When the RC clock is used, additional errors can occur because the comparator is sensitive to the additional system clock noise. M68HC11E Family — Rev. 5 MOTOROLA Analog-to-Digital (A/D) Converter Analog-to-Digital (A/D) Converter Overview Data Sheet ...
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... Unimplemented Analog-to-Digital (A/D) Converter Figure 3-3 shows the timing of BIT 2 BIT 1 LSB CYC CYC CYC CYC END CONVERT FOURTH CHANNEL, UPDATE 96 ADR4 128 — E CYCLES (1) (1) CME CR1 M68HC11E Family — Rev. 5 MOTOROLA Bit 0 (1) CR0 0 ...
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... E input lines to the MCU, four of the channels are internal reference points or test functions, and four channels are reserved. Refer to M68HC11E Family — Rev. 5 MOTOROLA Section 5. Resets and Interrupts. resumes processing within about four bus cycles. started up from the stop power-saving mode. This delay allows the crystal oscillator to stabilize ...
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... AN5 7 AN6 8 AN7 9 – 12 Reserved ( ( ( )/2 RH (1) 16 Reserved 1. Used for factory testing Analog-to-Digital (A/D) Converter Result in ADRx if MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 — ADR1 ADR2 ADR3 ADR4 M68HC11E Family — Rev. 5 MOTOROLA ...
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... MULT — Multiple Channel/Single Channel Control Bit When this bit is clear, the A/D converter system is configured to perform four consecutive conversions on the single channel specified by the four channel select bits CD:CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D M68HC11E Family — Rev. 5 MOTOROLA Bit ...
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... E clock of 2 MHz. The RC charging rate of the external circuit must be balanced against this charge sharing effect to avoid errors in accuracy. Refer to M68HC11 Reference Manual, Motorola document order number M68HC11RM/AD, for further information. CD:CA — Channel Selects D:A Bits Refer to two least significant channel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four channels converted ...
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... Register name: Analog-to-Digital Converter Result Register 2 Read: Write: Reset: Register name: Analog-to-Digital Converter Result Register 3 Read: Write: Reset: Register name: Analog-to-Digital Converter Result Register 4 Read: Write: Reset: M68HC11E Family — Rev. 5 MOTOROLA Bit Bit 7 Bit 6 Bit 5 Bit 4 Indeterminate after reset Bit ...
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... Analog-to-Digital (A/D) Converter Data Sheet 72 Analog-to-Digital (A/D) Converter M68HC11E Family — Rev. 5 MOTOROLA ...
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... M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed in the following paragraphs, are shown in M68HC11E Family — Rev. 5 MOTOROLA Section 4. Central Processor Unit (CPU) Central processor unit (CPU) architecture Data types ...
Page 74
... Central Processor Unit (CPU) 8-BIT ACCUMULATORS A & 16-BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER CONDITION CODES CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE M68HC11E Family — Rev. 5 MOTOROLA ...
Page 75
... A off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. M68HC11E Family — Rev. 5 MOTOROLA 4.4 Opcodes and Operands Figure 4 summary of SP operations. ...
Page 76
... MAIN PROGRAM 7 $3F = SWI SP–9 SP–8 CCR ACCB SP–7 SP–6 ACCA IX SP–5 H SP– MAIN PROGRAM IY SP–3 H SP–2 IY $3E = WAI L RTN SP–1 H RTN SP L Clock Monitor COP Watchdog $FFFC, D $FFFA, B $BFFC, D $BFFA, B M68HC11E Family — Rev. 5 MOTOROLA 0 0 ...
Page 77
... Interrupt Mask (I) The interrupt request (IRQ) mask (I bit global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending, but the M68HC11E Family — Rev. 5 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) CPU Registers ...
Page 78
... S is set by reset; STOP is disabled by default. 4.3 Data Types The M68HC11 CPU supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses Data Sheet 78 Interrupts. Central Processor Unit (CPU) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 79
... There are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction. M68HC11E Family — Rev. 5 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Opcodes and Operands ...
Page 80
... For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Data Sheet 80 4-2, which shows all the M68HC11 instructions in all possible Central Processor Unit (CPU) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 81
... Right A b7 ASRB Arithmetic Shift Right B b7 BCC (rel) Branch if Carry ? Clear M • (mm) ⇒ M BCLR (opr) Clear Bit(s) (msk) BCS (rel) Branch if Carry ? Set M68HC11E Family — Rev. 5 MOTOROLA Addressing Instruction Mode Opcode INH 1B INH 3A INH IMM 89 A DIR 99 A ...
Page 82
... M68HC11E Family — Rev. 5 MOTOROLA C — — — — — — — — — — — — — — — — — — — — ...
Page 83
... Memory B ⊕ M ⇒ B EORB (opr) Exclusive OR B with Memory ⇒ IX; r ⇒ D FDIV Fractional Divide ⇒ IX; r ⇒ D IDIV Integer Divide M68HC11E Family — Rev. 5 MOTOROLA Addressing Instruction Mode Opcode Operand ii A IMM DIR 91 hh ...
Page 84
... M68HC11E Family — Rev. 5 MOTOROLA C — — — — — — — — — — — — — — ∆ ∆ ∆ ∆ ...
Page 85
... ⇐ Stk PULY Pull Y from Stack (Hi First) ROL (opr) Rotate Left C b7 ROLA Rotate Left ROLB Rotate Left ROR (opr) Rotate Right b7 M68HC11E Family — Rev. 5 MOTOROLA Addressing Instruction Mode Opcode EXT 74 IND,X 64 IND INH INH ...
Page 86
... M68HC11E Family — Rev. 5 MOTOROLA C ∆ ∆ ∆ — ∆ ∆ ∆ 1 — — — — — — — — — ∆ ∆ ∆ ...
Page 87
... Boolean AND + Arithmetic addition symbol except where used as inclusive-OR symbol in Boolean formula ⊕ Exclusive-OR ∗ Multiply : Concatenation – Arithmetic subtraction symbol or negation symbol (two’s complement) M68HC11E Family — Rev. 5 MOTOROLA Addressing Instruction Mode Opcode Operand INH 3F — INH 16 — INH 06 — ...
Page 88
... Central Processor Unit (CPU) Data Sheet 88 Central Processor Unit (CPU) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 89
... RESET pin low whenever V below the minimum operating level. This external voltage level detector, or other external reset circuits, are the usual source of reset in a system. M68HC11E Family — Rev. 5 MOTOROLA Power-on reset (POR) External reset (RESET) Computer operating properly (COP) reset ...
Page 90
... E = 1.0 MHz 2.0 MHz Resets and Interrupts 15 and then further scaled by a XTAL = 12.0 MHz XTAL = 16.0 MHz Timeout Timeout – 0 ms, + 10.9 ms – 0 ms, + 8.2 ms 10.923 ms 8.19 ms 43.691 ms 32.8 ms 174.76 ms 131 ms 699.05 ms 524 ms 3.0 MHz 4.0 MHz M68HC11E Family — Rev. 5 MOTOROLA ...
Page 91
... CME bit in the OPTION register disable the clock monitor. After recovery from STOP, set the CME bit to logic 1 to enable the clock monitor. Alternatively, executing a STOP instruction with the CME bit set to logic 1 can be used as a software initiated reset. M68HC11E Family — Rev. 5 MOTOROLA $103A Bit ...
Page 92
... Section 3. Analog-to-Digital (A/D) Section 3. Analog-to-Digital (A/D) Section 2. Operating Modes and On-Chip Memory Converter. 15 for specific timeout settings. Resets and Interrupts Bit 0 (1) CME CR1 CR0 Converter. Converter. and Section 3. before it enters the COP watchdog M68HC11E Family — Rev. 5 MOTOROLA (1) ...
Page 93
... Depending on the cause of the reset and the operating mode, the reset vector can be fetched from any of six possible locations. Refer to Table 5-2. These initial states then control on-chip peripheral systems to force them to known startup states, as described in the following subsections. M68HC11E Family — Rev. 5 MOTOROLA $103F Bit EE3 EE2 ...
Page 94
... Pulse Accumulator The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin defaults to being a general-purpose input pin. Data Sheet 94 Section 2. Operating Modes and On-Chip Resets and Interrupts Memory. M68HC11E Family — Rev. 5 MOTOROLA ...
Page 95
... The clock monitor system is disabled because CME is cleared. M68HC11E Family — Rev. 5 MOTOROLA Section 2. Operating Modes and On-Chip for a detailed description of SMOD and MDA. The DLY control bit is set Resets and Interrupts ...
Page 96
... I bit in the CCR any associated local bits. Interrupt vectors are not affected by priority assignment. To avoid race conditions, HPRIO can be written only while I-bit interrupts are inhibited. Data Sheet 96 Figure 5-7) Resets and Interrupts M68HC11E Family — Rev. 5 MOTOROLA ...
Page 97
... PSEL[3:0] — Priority Select Bits These bits select one interrupt source to be elevated above all other I-bit-related sources and can be written only while the I bit in the CCR is set (interrupts disabled). M68HC11E Family — Rev. 5 MOTOROLA $103C Bit (1) ...
Page 98
... Timer input capture Timer output compare Timer output compare Timer output compare Timer output compare Timer input capture 4/output compare 5 Table Resets and Interrupts 5-4, which shows the interrupt M68HC11E Family — Rev. 5 MOTOROLA ...
Page 99
... FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF M68HC11E Family — Rev. 5 MOTOROLA Table 5-4. Interrupt and Reset Vector Assignments Interrupt Source SCI serial system • SCI receive data register full • SCI receiver overrun • SCI transmit data register empty • SCI transmit complete • ...
Page 100
... Section 4. Central Processor Unit Table 5-5. Stacking Order on Entry to Interrupts Memory Location SP SP–1 SP–2 SP–3 SP–4 SP–5 SP–6 SP–7 SP–8 Resets and Interrupts Table 5-5. After the CCR (CPU). CPU Registers PCL PCH IYL IYH IXL IXH ACCA ACCB CCR M68HC11E Family — Rev. 5 MOTOROLA ...
Page 101
... Figure 5-5 illustrates how the CPU begins from a reset and how interrupt detection relates to normal opcode fetches. illustrates interrupt priorities. within the SCI subsystem. M68HC11E Family — Rev. 5 MOTOROLA and Figure 5-6 illustrate the reset and interrupt process. Figure 5 expansion of a block in ...
Page 102
... BIT CCR = 1? N XIRQ Y PIN LOW Resets and Interrupts LOWEST PRIORITY COP WATCHDOG TIMEOUT (WITH NOCOP = 0) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFA, $FFFB (VECTOR FETCH) STACK CPU REGISTERS SET BITS I AND X FETCH VECTOR $FFF4, $FFF5 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 103
... REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 Figure 5-5. Processing Flow Out of Reset (Sheet M68HC11E Family — Rev. 5 MOTOROLA 2A Y BIT I IN CCR = 1? N ANY I-BIT Y INTERRUPT PENDING? N ...
Page 104
... NO YES YES FETCH VECTOR TIMER $FFEE, FFEF IC1F ? NO YES YES FETCH VECTOR TIMER $FFEC, FFED IC2F ? NO YES YES FETCH VECTOR TIMER $FFEA, FFEB IC3F ? NO YES YES FETCH VECTOR TIMER $FFE8, FFE9 OC1F ? NO Resets and Interrupts 2B M68HC11E Family — Rev. 5 MOTOROLA ...
Page 105
... Y PAOVI = PAII = SPIE = 1? N SCI Y INTERRUPT? SEE FIGURE 5–3 N Figure 5-6. Interrupt Priority Resolution (Sheet M68HC11E Family — Rev. 5 MOTOROLA Y FLAG FETCH VECTOR OC2F = 1? $FFE6, $FFE7 N Y FLAG FETCH VECTOR OC3F = 1 $FFE4, $FFE5 N Y FLAG FETCH VECTOR OC4F = 1? $FFE2, $FFE3 ...
Page 106
... IDLE = VALID SCI REQUEST Figure 5-7. Interrupt Source Resolution Within SCI Data Sheet 106 Y RIE = TIE = TCIE = ILIE = Resets and Interrupts VALID SCI REQUEST M68HC11E Family — Rev. 5 MOTOROLA ...
Page 107
... The CPU state and I/O pin levels are static and are unchanged by stop. Therefore, when an interrupt comes to restart the system, the MCU resumes processing as if there were no interruption. If reset is used to restart the system, a normal reset M68HC11E Family — Rev. 5 MOTOROLA Resets and Interrupts Resets and Interrupts Low-Power Operation power is maintained ...
Page 108
... This same delay also applies to power-on reset, regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are running. Data Sheet 108 Resets and Interrupts M68HC11E Family — Rev. 5 MOTOROLA ...
Page 109
... Reset states for these bits are indicated with a U. 6.2 Port A Port A shares functions with the timer system and has: • • • M68HC11E Family — Rev. 5 MOTOROLA Section 6. Parallel Input/Output (I/O) Ports Table 6-1. Input/Output Ports Input Output Bidirectional Pins ...
Page 110
... System. Section 9. Timing System. Section 9. Timing System. Section 9. Timing System. Parallel Input/Output (I/O) Ports Bit 0 PA3 PA2 PA1 PA0 IC4/OC5 IC1 IC2 IC3 OC1 — — — Bit 0 DDRA3 I4/O5 RTR1 RTR0 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 111
... C register address is treated as an external memory location. Address: Single-chip or bootstrap modes: Read: Write: Reset: Expanded or special test modes: Read: Write: Reset: M68HC11E Family — Rev. 5 MOTOROLA $1004 Bit PB7 PB6 PB5 PB4 ADDR15 ...
Page 112
... Figure 6-7. Port D Data Register (PORTD) Parallel Input/Output (I/O) Ports Bit 0 PCL3 PCL2 PCL1 PCL0 Bit 0 DDRC3 DDRC2 DDRC1 DDRC0 Bit 0 PD3 PD2 PD1 PD0 PD3 PD2 PD1 PD0 MOSI MISO Tx RxD M68HC11E Family — Rev. 5 MOTOROLA ...
Page 113
... Port C levels are latched into the alternate port C latch (PORTCL) register on each assertion of the STRA input. STRA edge select, flag, and interrupt enable bits are located in the PIOC register. Any or all of the port C lines can still be used as general-purpose I/O while in strobed input mode. M68HC11E Family — Rev. 5 MOTOROLA $1009 Bit ...
Page 114
... Parallel Input/Output (I/O) Ports for Table 6-2 Port B Port C Inputs latched into STRB pulses PORTCL on any on writes active edge on to PORTB STRA Inputs latched into Normal output PORTCL on any port, unaffected active edge on in handshake STRA modes M68HC11E Family — Rev. 5 MOTOROLA ...
Page 115
... Simple strobe mode 1 = Full input or output handshake mode OIN — Output or Input Handshake Select Bit HNDS must be set to 1 for this bit to have meaning Input handshake 1 = Output handshake M68HC11E Family — Rev. 5 MOTOROLA Table 6-2. Parallel I/O Control (Continued) OIN PLS 0 = STRB 0 active level ...
Page 116
... STRA falling edge selected, high level activates port C outputs (output 1 = STRA rising edge selected, low level activates port C outputs (output INVB — Invert Strobe B Bit 0 = Active level is logic Active level is logic 1. Data Sheet 116 handshake) handshake) Parallel Input/Output (I/O) Ports M68HC11E Family — Rev. 5 MOTOROLA ...
Page 117
... The contents of the serial shift register can be written only through the SCDR. This double buffered operation allows a character to be shifted out serially while another character is waiting in the SCDR to be transferred into the M68HC11E Family — Rev. 5 MOTOROLA Section 7. Serial Communications Interface (SCI) Figure 7-8 and character start bit, a character of eight or nine data bits, and a stop bit ...
Page 118
... DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 for an example of connecting TxD to a PC. Serial Communications Interface (SCI) Figure 7-1, DDD1 SEE NOTE PD1 PIN BUFFER TxD AND CONTROL 8 8 INTERNAL DATA BUS M68HC11E Family — Rev. 5 MOTOROLA ...
Page 119
... This type of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time between frames in a message. M68HC11E Family — Rev. 5 MOTOROLA Serial Communications Interface (SCI) Serial Communications Interface (SCI) Receive Operation Figure 7-2 ...
Page 120
... LOGIC SCSR SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 for an example of connecting RxD to a PC. Serial Communications Interface (SCI) 10 (11) - BIT Rx SHIFT REGISTER MSB ALL 1s RWU 8 SCDR Rx BUFFER READ ONLY 8 8 INTERNAL DATA BUS M68HC11E Family — Rev. 5 MOTOROLA ...
Page 121
... SCDR until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of the SCDR. M68HC11E Family — Rev. 5 MOTOROLA Serial Communications Interface (SCI) Serial Communications Interface (SCI) SCI Error Detection ...
Page 122
... Baud rate register (BAUD) Serial communications status register (SCSR) Serial communications data register (SCDR) Register, Figure 7-8, and $102F Bit R7/T7 R6/T6 R5/T5 R4/T4 Indeterminate after reset Figure 7-3. Serial Communications Data Register (SCDR) Serial Communications Interface (SCI) Figure 7- Bit 0 R3/T3 R2/T2 R1/T1 R0/T0 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 123
... Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE — Wakeup by Address Mark/Idle Bit 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mark (most significant data bit set) Bits [2:0] — Unimplemented Always read 0 M68HC11E Family — Rev. 5 MOTOROLA $102C Bit ...
Page 124
... SBK Break generator off 1 = Break codes generated Data Sheet 124 $102D Bit TIE TCIE RIE ILIE Serial Communications Interface (SCI Bit RWU SBK M68HC11E Family — Rev. 5 MOTOROLA ...
Page 125
... OR — Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR overrun 1 = Overrun detected M68HC11E Family — Rev. 5 MOTOROLA $102E Bit TDRE TC ...
Page 126
... Bit TCLR SCP2 SCP1 SCP0 Unaffected Figure 7-7. Baud Rate Register (BAUD) Figure 7-8 and Figure Serial Communications Interface (SCI Bit 0 RCKB SCR2 SCR1 SCR0 7-9. M68HC11E Family — Rev. 5 MOTOROLA ...
Page 127
... Shaded areas reflect standard baud rates. On MC68HC(7)11E20 do not set SCP1 or SCP0 when SCP2 is 1. M68HC11E Family — Rev. 5 MOTOROLA Table 7-1. Baud Rate Values Baud 4.00 4.9152 Prescale Set Divide Divide 1. 62500 76800 ...
Page 128
... Figure 7-8. SCI Baud Rate Generator Block Diagram Serial Communications Interface (SCI) 7-9. INTERNAL BUS CLOCK (PH2) ÷ ÷ ÷ SCP[1:0] 0:1 1:0 1:1 SCR[2:0] 0:0:0 0:0:1 0:1:0 0:1:1 ÷ 16 1:0:0 SCI TRANSMIT 1:0:1 BAUD RATE (1X) 1:1:0 1:1:1 SCI RECEIVE BAUD RATE (16X) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 129
... The software clearing sequence for M68HC11E Family — Rev. 5 MOTOROLA OSCILLATOR AND CLOCK GENERATOR (÷4) ...
Page 130
... The IDLE flag is set only after the RxD line has been busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle. Data Sheet 130 Serial Communications Interface (SCI) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 131
... RDRF = 1? VALID SCI REQUEST M68HC11E Family — Rev. 5 MOTOROLA BEGIN Y FLAG RIE = TDRE = 1? TIE = IDLE = 1? ILIE = Figure 7-10. Interrupt Source Resolution Within SCI Serial Communications Interface (SCI) Serial Communications Interface (SCI) Receiver Flags ...
Page 132
... Serial Communications Interface (SCI) Data Sheet 132 Serial Communications Interface (SCI) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 133
... The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR). Refer to M68HC11E Family — Rev. 5 MOTOROLA Section 8. Serial Peripheral Interface (SPI) Frequency synthesizers Liquid crystal display (LCD) drivers Analog-to-digital (A/D) converter subsystems ...
Page 134
... SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE SPI CONTROL REGISTER INTERNAL DATA BUS Figure 8-1. SPI Block Diagram Figure 8-2. Serial Peripheral Interface (SPI) S MISO PD2 M M MOSI PD3 S S SCK PD4 M SS PD5 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 135
... When CPHA equals 1, the SS line can remain low between successive transfers. 8.5 SPI Signals This subsection contains descriptions of the four SPI signals: • Master in/slave out (MISO) • Master out/slave in (MOSI) • Serial clock (SCK) • Slave select (SS) M68HC11E Family — Rev. 5 MOTOROLA MSB 6 5 ...
Page 136
... When CPHA = 0, the shift clock is the with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low Data Sheet 136 Serial Peripheral Interface (SPI) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 137
... SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals 1 when SPIF is set. M68HC11E Family — Rev. 5 MOTOROLA as long as only CPHA = 1 clock mode is used. SS Serial Peripheral Interface (SPI) ...
Page 138
... Slave mode 1 = Master mode Data Sheet 138 $1028 Bit SPIE SPE DWOM MSTR Unaffected Figure 8-3. Serial Peripheral Control Register (SPCR) Serial Peripheral Interface (SPI Bit 0 CPOL CPHA SPR1 SPR0 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 139
... If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited. M68HC11E Family — Rev. 5 MOTOROLA Figure 8-2 and 8.4 Clock Phase and Polarity Figure 8-2 Controls ...
Page 140
... Slave Select and 8.6 SPI System $102A Bit Bit 7 Bit 6 Bit 5 Bit 4 Indeterminate after reset Figure 8-5. Serial Peripheral Data I/O Register (SPDR) Serial Peripheral Interface (SPI) 8.5.4 Slave Select and 8.6 SPI Errors Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 141
... The real-time interrupt (RTI programmable periodic interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates. M68HC11E Family — Rev. 5 MOTOROLA Section 9. Timing System Timing System Figure 9-1. Data Sheet ...
Page 142
... CLEAR COP SYSTEM TIMER RESET Timing System AS E CLOCK INTERNAL BUS CLOCK (PH2) SPI SCI RECEIVER CLOCK ÷16 SCI TRANSMIT CLOCK PULSE ACCUMULATOR REAL-TIME INTERRUPT FF2 S Q FORCE R COP Q RESET E SERIES TIM DIV CHAIN M68HC11E Family — Rev. 5 MOTOROLA ...
Page 143
... A output pins. Output compare one (OC1) has extra control logic, allowing it optional control of any combination of the PA[7:3] pins. The PA7 pin can be used as a general-purpose I/O pin input to the pulse accumulator OC1 output pin. M68HC11E Family — Rev. 5 MOTOROLA Table 9-1 for crystal-related frequencies and periods. Table 9-1. Timer Summary 4.0 MHz 1 ...
Page 144
... QUALIFIED BY I BIT IN CCR) TO PULSE ACCUMULATOR PIN 8 FUNCTIONS PA7/OC1/ BIT 7 PAI 7 PA6/OC2/ BIT 6 OC1 6 PA5/OC3/ BIT 5 OC1 5 PA4/OC4/ BIT 4 OC1 4 PA3/OC5/ BIT 3 IC4/OC1 3 BIT 2 PA2/IC1 2 BIT 1 PA1/IC2 1 BIT 0 PA0/IC3 PORT A PIN CONTROL CAPTURE COMPARE BLOCK M68HC11E Family — Rev. 5 MOTOROLA ...
Page 145
... PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. M68HC11E Family — Rev. 5 MOTOROLA Timing System Timing System Input Capture Data Sheet ...
Page 146
... Table 9-2. Timer Control Configuration EDGxB EDGxA 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge Timing System Bit 0 EDG2B EDG2A EDG3B EDG3A Table 9-2 Configuration M68HC11E Family — Rev. 5 MOTOROLA for ...
Page 147
... Write: Reset: Register name: Timer Input Capture 3 Register (High) Read: Write: Reset: Register name: Timer Input Capture 3 Register (Low) Read: Write: Reset: M68HC11E Family — Rev. 5 MOTOROLA Address: $1010 Bit Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset Address: $1011 ...
Page 148
... Bit 6 Bit 5 Bit Figure 9-7. Timer Input Capture 4/Output Compare 5 Register Pair (TI4/O5) Timing System Address: $101E Bit 0 Bit 11 Bit 10 Bit 9 Bit Address: $101F Bit 0 Bit 3 Bit 2 Bit 1 Bit M68HC11E Family — Rev. 5 MOTOROLA ...
Page 149
... TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison value, specified pin actions occur. Register name: Timer Output Compare 1 Register (High) Read: Write: Reset: Register name: Timer Output Compare 1 Register (Low) Read: Write: Reset: M68HC11E Family — Rev. 5 MOTOROLA Bit Bit 15 Bit 14 Bit 13 Bit ...
Page 150
... Bit Address: $101C Bit 11 Bit 10 Bit Address: $101D Bit 3 Bit 2 Bit M68HC11E Family — Rev. 5 MOTOROLA Bit 0 Bit 8 1 Bit 0 Bit 0 1 Bit 0 Bit 8 1 Bit 0 Bit 0 1 Bit 0 Bit 8 1 Bit 0 Bit 0 1 ...
Page 151
... When the FOC bit associated with an output compare circuit is set, the output compare circuit immediately performs the action it is programmed to do when an output match occurs Not affected 1 = Output x action occurs Bits [2:0] — Unimplemented Always read 0 M68HC11E Family — Rev. 5 MOTOROLA $100B Bit FOC1 FOC2 ...
Page 152
... Unimplemented Figure 9-13. Output Compare 1 Mask Register (OC1M) $100D Bit OC1D7 OC1D6 OC1D5 OC1D4 Unimplemented Figure 9-14. Output Compare 1 Data Register (OC1D) Timing System Bit 0 OC1M3 Bit 0 OC1D3 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 153
... OM[2:5] — Output Mode Bits OL[2:5] — Output Level Bits These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to M68HC11E Family — Rev. 5 MOTOROLA Address: $100E Bit ...
Page 154
... Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1) $1023 Bit OC1F OC2F OC3F OC4F Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1) Timing System Bit 0 I4/O5I IC1I IC2I IC3I Bit 0 I4/O5F IC1F IC2F IC3F M68HC11E Family — Rev. 5 MOTOROLA ...
Page 155
... PR[1:0] can be written only once, and the write must be within 64 cycles after reset. Refer to NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable the corresponding interrupt sources. M68HC11E Family — Rev. 5 MOTOROLA $1024 Bit TOI ...
Page 156
... Accumulator. 9.7 Pulse Accumulator. Table 9-5. RTI Rates MHz MHz 2.731 ms 4.096 ms 5.461 ms 8.192 ms 10.923 ms 16.384 ms 21.845 ms 32.768 ms Timing System Bit Table 9- MHz MHz 13 8.192 ms (E 16.384 ms (E 32.768 ms (E 65.536 ms (E/2 ) M68HC11E Family — Rev. 5 MOTOROLA ...
Page 157
... Bits [3:2] — Unimplemented Always read 0 PR[1:0] — Timer Prescaler Select Bits Refer to NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable the corresponding interrupt sources. M68HC11E Family — Rev. 5 MOTOROLA 9.4.9 Timer Interrupt Mask 2 2, and $1024 Bit ...
Page 158
... Refer to Bits [3:0] — Unimplemented Always read 0 Data Sheet 158 $1025 Bit TOF RTIF PAOVF PAIF Unimplemented Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2) 9.7 Pulse Accumulator. 9.7 Pulse Accumulator. Timing System Bit M68HC11E Family — Rev. 5 MOTOROLA ...
Page 159
... OPTION register and the NOCOP bit in the CONFIG register determine the status of the COP function. One additional register, COPRST, is used to arm and clear the COP watchdog reset system. Refer to more detailed discussion of the COP function. M68HC11E Family — Rev. 5 MOTOROLA Computer Operating Properly (COP) Watchdog Function $1026 Bit 7 6 ...
Page 160
... PAEN CLOCK : 2 1 MUX DATA BUS PAEN PACTL CONTROL INTERNAL DATA BUS Figure 9-24. Pulse Accumulator Timing System Table 9-6. The PAOVI PAOVF 1 INTERRUPT REQUESTS PAII PAIF 2 TFLG2 INTERRUPT STATUS DISABLE FLAG SETTING OVERFLOW PACNT 8-BIT COUNTER ENABLE M68HC11E Family — Rev. 5 MOTOROLA ...
Page 161
... PAMOD — Pulse Accumulator Mode Bit 0 = Event counter 1 = Gated time accumulation PEDGE — Pulse Accumulator Edge Control Bit This bit has different meanings depending on the state of the PAMOD bit, as shown in M68HC11E Family — Rev. 5 MOTOROLA Table 9-6. Pulse Accumulator Timing Crystal E Clock 4.0 MHz 1 MHz 8.0 MHz ...
Page 162
... Bit TOF RTIF PAOVF PAIF Unimplemented Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2) Timing System Ports Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 0 PR1 PR0 Bit M68HC11E Family — Rev. 5 MOTOROLA ...
Page 163
... When the PAII control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the interrupt service routine, software must clear PAIF by writing to the TFLG2 register. M68HC11E Family — Rev. 5 MOTOROLA Timing System Timing System Pulse Accumulator Data Sheet ...
Page 164
... Timing System Data Sheet 164 Timing System M68HC11E Family — Rev. 5 MOTOROLA ...
Page 165
... For proper operation recommended that constrained to the range V Out is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either V M68HC11E Family — Rev. 5 MOTOROLA Section 10. Electrical Characteristics 10.5 DC Electrical Characteristics, 10.7 MC68L11E9/E20 DC Electrical Rating (1) excluding V ...
Page 166
... V Value Unit + (P × Θ ° °C User-determined 50 50 °C INT I 273° × User-determined W × 273° W/°C + Θ × (at equilibrium). Use this value D M68HC11E Family — Rev. 5 MOTOROLA ...
Page 167
... specification for RESET and MODA is not applicable because they are open-drain pins applicable to ports C and D in wired-OR mode. 3. Refer to 10.13 Analog-to-Digital Converter Characteristics Characteristics for leakage current for port E. M68HC11E Family — Rev. 5 MOTOROLA (1) Symbol ...
Page 168
... DD W IDD S IDD unless otherwise noted Electrical Characteristics Min Max Unit — 15 — — 27 — 35 — 6 — — 10 — 20 — 25 µA — 50 — 100 — 85 — 150 mW — 150 — 195 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 169
... RESET and MODA is not applicable because they are open-drain pins applicable to ports C and D in wired-OR mode. 3. Refer to 10.13 Analog-to-Digital Converter Characteristics Characteristics for leakage current for port E. M68HC11E Family — Rev. 5 MOTOROLA MC68L11E9/E20 DC Electrical Characteristics (1) Symbol ...
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... Data Sheet 170 (1) Symbol IDD S IDD unless otherwise noted Electrical Characteristics 1 MHz 2 MHz Unit 1 2.5 5 µ 150 21 42 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 171
... Notes: 1. Full test loads are applied during all dc electrical tests and ac timing measurements. 2. During ac timing measurements, inputs are driven to 0.4 volts and V measurements are taken at 20% and 70 M68HC11E Family — Rev. 5 MOTOROLA MC68L11E9/E20 Supply Currents and Power Dissipation 0.4 VOLTS 0.4 VOLTS ~ V SS ...
Page 172
... CYC — 1 — 1 — t — 2 — 2 — CYC — 10 — 10 — ns — 520 — 353 — — 4 — 4 CYC — 520 — 353 — ns and 70 unless DD DD Section 5. M68HC11E Family — Rev. 5 MOTOROLA ...
Page 173
... PA7 (2) (3) PA7 Notes : 1. Rising edge sensitive input 2. Falling edge sensitive input 3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2. M68HC11E Family — Rev. 5 MOTOROLA (1) ( all timing is shown with respect to 20 TIM Figure 10-2. Timer Inputs ...
Page 174
V DD EXTAL 4064 t CYC E RESET MODA, MODB FFFE FFFE FFFE ADDRESS Figure 10-3. POR External Reset Timing Diagram t PCSU PW RSTL t MPS NEW FFFE FFFF FFFE FFFE FFFE PC t MPH NEW FFFE FFFE FFFF ...
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INTERNAL CLOCKS 1 IRQ PW IRQ IRQ or XIRQ t STOPDELAY E STOP STOP 4 ADDRESS ADDR ADDR + 1 5 STOP STOP ADDRESS ADDR ADDR + 1 Notes : 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. ...
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E IRQ, XIRQ, OR INTERNAL INTERRUPTS WAIT WAIT ADDRESS SP SP – – 2…SP – 8 ADDR ADDR + 1 PCL PCH, YL, YH, XL, XH CCR STACK REGISTERS R/W Note: RESET also causes recovery from ...
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E t PCSU 1 IRQ PW IRQ 2 IRQ , XIRQ, OR INTERNAL INTERRUPT NEXT NEXT ADDRESS SP OPCODE DATA – – PCL CODE R/W Notes : 1. Edge sensitive IRQ pin (IRQE bit = 1) ...
Page 178
... V , unless DD DD M68HC11E Family — Rev. 5 MOTOROLA ...
Page 179
... Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respectively this setup time is met, STRB acknowledges in the next cycle not met, the response may be delayed one more cycle. M68HC11E Family — Rev. 5 MOTOROLA (1) (2) Symbol f ...
Page 180
... MCU WRITE TO PORT PWD PWD READ PORTCL READ PORTCL t t DEB DEB t t AES AES Electrical Characteristics NEW DATA VALID NEW DATA VALID t t DEB DEB 1 ( DEB DEB PORT C INPUT HNDSHK TIM M68HC11E Family — Rev. 5 MOTOROLA ...
Page 181
... After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). Figure 10-13. 3-State Variation of Output Handshake Timing Diagram M68HC11E Family — Rev. 5 MOTOROLA 1 (1) WRITE PORTCL t ...
Page 182
... CYC µs t +32 t +32 — CYC CYC Guaranteed — — — — — — Hex — Hex t 12 — — CYC µs — typical — — pF — 400 400 nA µA — 1.0 1 ±10%. R M68HC11E Family — Rev. 5 MOTOROLA ...
Page 183
... Input leakage on A/D pins PE[7:0] Input leakage 3.0 Vdc to 5.5 Vdc Vdc Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage. M68HC11E Family — Rev. 5 MOTOROLA MC68L11E9/E20 Analog-to-Digital Converter Characteristics (2) Parameter V and 750 kHz ≤ ...
Page 184
... V , unless DD DD M68HC11E Family — Rev. 5 MOTOROLA Unit MHz ...
Page 185
... To recalculate the approximate bus timing values, substitute the following expressions in place of 1 the above formulas, where applicable: CYC (a) (1–dc) × 1/4 t CYC (b) dc × 1/4 t CYC Where the decimal value of duty cycle percentage (high time). M68HC11E Family — Rev. 5 MOTOROLA MC68L11E9/E20 Expansion Bus Timing Characteristics (1) –25 ns CYC –30 ns CYC = 1/8 t –30 ns CYC (2)a ...
Page 186
... Data Sheet 186 ADDRESS ADDRESS 19 19 ADDRESS ADDRESS Electrical Characteristics DATA DATA 21 21 DATA DATA MUX BUS TIM M68HC11E Family — Rev. 5 MOTOROLA ...
Page 187
... Vdc ±10 Vdc otherwise noted 2. Time to data active from high-impedance state 3. Assumes 200 pF load on SCK, MOSI, and MISO pins M68HC11E Family — Rev. 5 MOTOROLA Serial Peripheral Interface Timing Characteristics E9 Symbol Min 333 CYC ...
Page 188
... CYC t 1 — CYC t – CYC CYC 1/2 t –30 — CYC t – CYC CYC 1/2 t –30 — CYC 40 — — 40 — — — — — ns and 70 unless DD DD M68HC11E Family — Rev. 5 MOTOROLA ...
Page 189
... CPOL = 1 OUTPUT MISO INPUT MOSI OUTPUT Note: This first clock edge is generated internally but is not seen at the SCK pin. Figure 10-15. SPI Timing Diagram (Sheet M68HC11E Family — Rev. 5 MOTOROLA MC68L11E9/E20 Serial Peirpheral Interface Characteristics SS IS HELD HIGH ON MASTER BIT 6 ...
Page 190
... A) SPI Slave Timing (CPHA = BIT MSB OUT SLAVE BIT MSB IN B) SPI Slave Timing (CPHA = 1) Electrical Characteristics 3 9 SEE SLAVE LSB OUT NOTE 11 11 LSB SLAVE LSB OUT 11 LSB IN M68HC11E Family — Rev. 5 MOTOROLA ...
Page 191
... During EPROM programming of the MC68HC711E9 device, the V input current is not limited to 10 mA. For more information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set Errata 3 (Motorola document order number 68HC711E9MSE3. 3. Typically, a 1-kΩ series resistor is sufficient to limit the programming current for the MC68HC711E9. A 100-Ω series resistor is sufficient to limit the programming current for the MC68HC711E20. M68HC11E Family — ...
Page 192
... Electrical Characteristics Data Sheet 192 Electrical Characteristics M68HC11E Family — Rev. 5 MOTOROLA ...
Page 193
... Description 52-pin plastic leaded chip carrier (PLCC) BUFFALO ROM No ROM No ROM, no EEPROM M68HC11E Family — Rev. 5 MOTOROLA Standard devices Custom ROM devices Extended voltage devices 52-pin plastic-leaded chip carrier (PLCC) 52-pin windowed ceramic-leaded chip carrier (CLCC) 64-pin quad flat pack (QFP) 52-pin thin quad flat pack (TQFP) 56-pin shrink dual in-line package with ...
Page 194
... MHz MC68HC811E2FN2 2 MHz MC68HC811E2CFN2 2 MHz MC68HC811E2VFN2 2 MHz MC68HC811E2MFN2 2 MHz MC68HC11E9BCFU2 3 MHz MC68HC11E9BCFU3 2 MHz MC68HC11E1CFU2 3 MHz MC68HC11E1CFU3 2 MHz MC68HC11E1VFU2 2 MHz MC68HC11E0CFU2 2 MHz MC68HC11E0VFU2 3 MHz MC68HC711E20FU3 2 MHz MC68HC711E20CFU2 3 MHz MC68HC711E20CFU3 2 MHz MC68HC711E20VFU2 2 MHz MC68HC711E20MFU2 2 MHz MC68HC11E9BCPB2 3 MHz MC68HC11E9BCPB3 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 195
... MC68HC811E2 only No ROM, 2 Kbytes EEPROM 56-pin dual in-line package with 0.70-inch lead spacing (SDIP) BUFFALO ROM No ROM No ROM, no EEPROM M68HC11E Family — Rev. 5 MOTOROLA Ordering Information and Mechanical Specifications CONFIG Temperature –40°C to +85°C $0F –40°C to +105°C – ...
Page 196
... MHz MC Order Number MC68HC11E9FN3 MC68HC11E9CFN2 MC68HC11E9CFN3 MC68HC11E9VFN2 MC68HC11E9MFN2 MC68HC11E20FN3 MC68HC11E20CFN2 MC68HC11E20CFN3 MC68HC11E20VFN2 MC68HC11E20MFN2 MC68HC11E9FU3 MC68HC11E9CFU2 MC68HC11E9CFU3 MC68HC11E9VFU2 MC68HC11E9MFU2 MC68HC11E20FU3 MC68HC11E20CFU2 MC68HC11E20CFU3 MC68HC11E20VFU2 MC68HC11E20MFU2 MC68HC11E9PB3 MC68HC11E9CPB2 MC68HC11E9CPB3 MC68HC11E9VPB2 MC68HC11E9MPB2 MC68HC11E9B3 MC68HC11E9CB2 MC68HC11E9CB3 MC68HC11E9VB2 MC68HC11E9MB2 M68HC11E Family — Rev. 5 MOTOROLA ...
Page 197
... No ROM, no EEPROM 56-pin dual in-line package with 0.70-inch lead spacing (SDIP) Custom ROM No ROM No ROM, no EEPROM M68HC11E Family — Rev. 5 MOTOROLA Ordering Information and Mechanical Specifications Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc) Temperature –20°C to +70°C –20°C to +70°C – ...
Page 198
... R 0.750 0.756 19.05 19.20 U 0.750 0.756 19.05 19.20 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0. 0.710 0.730 18.04 18.54 K1 0.040 ––– 1.02 ––– M68HC11E Family — Rev. 5 MOTOROLA ...
Page 199
... Windowed Ceramic-Leaded Chip Carrier (Case 778B) -A- R 0.51 (0.020 M68HC11E Family — Rev. 5 MOTOROLA Ordering Information and Mechanical Specifications 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B) 0.51 (0.020 - 0.15 (0.006) -T- SEATING PLANE ...
Page 200
... 0.130 0.170 0.005 0.007 P 0.40 BSC 0.016 BSC 0.13 0.30 0.005 0.012 S 16.20 16.60 0.638 0.654 T 0.20 REF 0.008 REF ––– 0 ––– V 16.20 16.60 0.638 0.654 X 1.10 1.30 0.043 0.051 M68HC11E Family — Rev. 5 MOTOROLA ...