RJ80530KZ933512 Intel Corporation, RJ80530KZ933512 Datasheet
RJ80530KZ933512
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RJ80530KZ933512 Summary of contents
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Low Voltage Intel Processor with 512KB L2 Cache Product Features Available at 800, 933, and 1000 MHz with a 133 MHz system bus frequency at 1.15 V (LV) 512-Kbyte Advanced Transfer Cache (on- die, full speed level two (L2) cache ...
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... OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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Contents 1.0 Introduction.................................................................................................................................... 7 1.1 Overview............................................................................................................................... 7 1.2 Terminology .......................................................................................................................... 8 1.3 Related Documents ..............................................................................................................9 2.0 Processor Features .....................................................................................................................10 2.1 512-Kbyte On-Die Integrated L2 Cache .............................................................................10 2.2 Data Prefetch Logic ............................................................................................................10 2.3 Processor System Bus and V 2.4 Differential Clocking ...
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Contents 4.0 System Signal Simulations......................................................................................................... 40 4.1 System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal Quality Specifications .......................................................... 40 4.2 AGTL AC Signal Quality Specifications .............................................................................. 42 4.3 Non-AGTL Signal Quality Specifications ............................................................................ 43 4.3.1 PWRGOOD Signal ...
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Tables 1 Related Documents ...................................................................................................................... 9 2 LV/ULV Intel® Pentium® III Processor 512K CPUID .................................................................15 3 System Bus Signal Groups.........................................................................................................16 4 BSEL[1:0] Encoding.................................................................................................................... Intel Pentium Processor 512K VID Values ........................................................................22 III 6 LV Intel Pentium Processor 512K Absolute ...
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Contents Revision History Date March 2002 September 2002 September 2002 January 2003 January 2003 6 Revision -001 First release of this document. -002 Added 933MHz data and 06B4 stepping -003 Added Chapter 6 and 7 -004 Added 1000MHz data -005 ...
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Introduction Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Low Voltage ® (LV) Intel Pentium Key performance features include Internet Streaming SIMD instructions, an Advanced Transfer Cache architecture, and a processor system bus speed ...
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LV Intel Pentium III Processor 512K 1.2 Terminology Term A “#” symbol following a signal name indicates that the signal is active low. This means that when the signal is asserted (based on the name of the signal) ...
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Related Documents Table 1. Related Documents P6 Family of Processors Hardware Developer’s Manual ® IA-32 Intel Architecture Software Developer’s Manual • Volume I: Basic Architecture • Volume II: Instruction Set Reference • Volume III: System Programming Guide VRM 8.5 ...
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LV Intel Pentium III Processor 512K 2.0 Processor Features 2.1 512-Kbyte On-Die Integrated L2 Cache The LV Intel Pentium L2 cache runs at the processor core speed and the increased cache size provides superior processing power. 2.2 Data ...
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Note: The RESET# signal requires a discrete external termination resistor on the system board. The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings. Analog signal ...
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LV Intel Pentium III Processor 512K Figure 2. Stop Clock State Machine 2. Auto HALT Power Down State BCLK running Snoops and interrupts allowed Snoop Event Occurs 4. HALT/Grant Snoop State BCLK running Service snoops to caches For ...
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FLUSH# is serviced during the AutoHALT state. Once the FLUSH# is complete the processor returns to the AutoHALT state. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the ...
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LV Intel Pentium III Processor 512K If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# ball specification, then the processor will reset itself, ignoring the transition ...
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Figure 3. Differential/Single-Ended Clocking Example Clock Driver Clock Driver 2.8 Processor System Bus Unused Balls All RESERVED balls must remain unconnected unless specifically noted. Connection of these balls CORE component malfunction or incompatibility with future ...
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LV Intel Pentium III Processor 512K 3.0 Electrical Specifications 3.1 Processor System Bus Signal Groups To simplify the following discussion, the processor system bus signals have been combined into groups by buffer type. All P6 family processor system ...
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Table 3. System Bus Signal Groups (Sheet APIC Clock APIC I/O Thermal Diode TAP Input TAP Output Power/Other NOTES the power supply for the core logic. CCCORE 2. PLL1 and PLL2 are power/ground for ...
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LV Intel Pentium III Processor 512K Figure 4. Single Ended Clock BSEL Circuit (133 MHz) NC BSEL0 BSEL1 Processor 1 3.3 Differential Host Bus Clocking Routing LV Intel Pentium III drivers. When operating in differential clocking mode, the ...
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Figure 5. Differential Clock BSEL Circuit 1K ohm 3.4 Signal State in Low-Power States 3.4.1 System Bus Signals All of the system bus signals have AGTL input, output, or input/output drivers. The system bus signals are tri-stated and pulled up ...
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LV Intel Pentium III Processor 512K 3.5 Test Access Port (TAP) Connection The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage levels supported by the TAP interface, Intel recommends that the ...
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For additional decoupling requirements, please refer to the appropriate platform design guide for recommended capacitor component value/quantity and placement. 3.6.3 Voltage Planes All V and V CC CORE balls must be connected to the appropriate traces on the system electronics. ...
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LV Intel Pentium III Processor 512K Table 5. LV Intel Pentium VID25mV ...
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The VID balls should be pulled 3.3-V level. This may be accomplished with pull-ups internal to the voltage regulator, which ensures valid VID pull-up voltage during power-up and power-down sequences. When external resistors are used for the ...
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LV Intel Pentium III Processor 512K 3.8 System Bus Clock and Processor Clocking The BCLK and BCLK# clock inputs directly control the operating speed of the system bus interface. All system bus timing parameters are specified with respect ...
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DC Specifications Tables 7 through 11 Specifications are valid only while meeting specifications for the junction temperature, clock frequency, and input voltages. The junction temperature range for all DC specifications is 0° 100° C. Care should be ...
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LV Intel Pentium III Processor 512K Figure 8. Power Supply Current Slew Rate (dI S lew R ate – 26A Load S tep Slew R ate (26A) – socket ...
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Table 8. V Static and Transient Tolerance CC CORE I CC (A) Static Min 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 Figure 9. V Static and Transient Tolerance CC CORE 60 ...
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LV Intel Pentium III Processor 512K Table 9. AGTL Signal Group Levels Specifications Symbol V Input Low Voltage IL V Input High Voltage IH Ron Buffer On Resistance Leakage Current for inputs outputs, and I/O NOTES: ...
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Table 11. CLKREF, APIC, TAP, CMOS, and Open-Drain Signal Group DC Specifications Symbol V Input Low Voltage, 1.5 V CMOS IL15 V Input Low Voltage, 1.8 V CMOS IL18 V Input High Voltage, 1.5 V CMOS IH15 Input High Voltage, ...
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LV Intel Pentium III Processor 512K 3.11 AC Specifications 3.11.1 System Bus, Clock, APIC, TAP, CMOS, and Open-Drain AC Specifications The processor system bus timings specified in this section are defined at the processor core (pads). All system ...
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Table 13. System Bus Clock AC Specifications (133 MHz, Single-Ended) Symbol System Bus Frequency T1S BCLK Period BCLK Period – Instantaneous T1Sabs Minimum T2S BCLK Period Stability T3S BCLK High Time T4S BCLK Low Time T5S BCLK Rise Time T6S ...
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LV Intel Pentium III Processor 512K Table 14. Valid LV Intel Pentium BCLK Frequency (MHz) 133 133 133 NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other than those listed above will ...
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Table 17. Reset Configuration AC Specifications and Power On Timings Symbol Reset Configuration Signals (A[15:5]#, T16 BR0#, FLUSH#, INIT#, PICD0) Setup Time Reset Configuration Signals (A[15:5]#, T17 BR0#, FLUSH#, INIT#, PICD0) Hold Time T18 RESET#/PWRGOOD Setup Time T18A V to ...
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LV Intel Pentium III Processor 512K Table 19. TAP Signal AC Specifications Symbol T30 TCK Frequency T31 TCK Period T32 TCK High Time T33 TCK Low Time T34 TCK Rise Time T35 TCK Fall Time T36 TRST# Pulse ...
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Figure 10. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform CLK NOTES T5S, T5S1, T34, T25 (Rise Time T6S, T6S1, T35, T26 (Fall Time T3S, T3S1, T32, T23 (High Time ...
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LV Intel Pentium III Processor 512K Figure 12. BCLK/BCLK# Waveform (Differential Mode) V IH_DIFF Il_DIFF Figure 13. Valid Delay Timings CLK Signal NOTES T7, T11, T29 (Valid Delay T14, ...
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Figure 14. Setup and Hold Timings CLK Signal NOTES T12, T27 (Setup Time T9, T13, T28 (Hold Time for AGTL signals; 1.0 V for CMOS, APIC, and TAP signals ...
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LV Intel Pentium III Processor 512K Figure 16. Power-On Sequence and Reset Timings BCLK/BCLK CCT VTTPWRGD VTT_PWRGD VID[3:0, 25mV]/ VID[4:0]/ BSEL[1:0] V CMOSREF/ CMOS_REF CLKREF/V REF CORE CC PWRGOOD RESET# NOTES: T ...
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Figure 17. Test Timings (Boundary Scan) TCK TDI, TMS Input Signals TDO Output Signals NOTES T43 (All Non-Test Inputs Setup Time T44 (All Non-Test Inputs Hold Time T40 (TDO Float Delay) u ...
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LV Intel Pentium III Processor 512K 4.0 System Signal Simulations Systems must be simulated using the LV Intel Pentium determine if they are compliant with this specification. All references to BCLK signal quality also apply to BCLK# for ...
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Table 22. PICCLK DC Specifications and AC Signal Quality Specifications Symbol V1 V IL20 V2 V IH20 V3 V Absolute Voltage Range IN V4 PICCLK Rising Edge Ringback V5 PICCLK Falling Edge Ringback NOTES: 1. The clock must rise/fall monotonically ...
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LV Intel Pentium III Processor 512K 4.2 AGTL AC Signal Quality Specifications The ringback specifications for the AGTL signals are as follows: • Ringback below V • Ringback above V Overshoot and undershoot specifications are documented in Figure ...
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Table 23. 133 MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core Max V + Overshoot/Undershoot TT Magnitude (volts) 1.78 1.73 1.68 1.63 1.58 1.53 1.48 NOTES: 1. Under no circumstances should the sum of the Max V voltage ...
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LV Intel Pentium III Processor 512K 4.3.1 PWRGOOD Signal Quality Specification The processor requires PWRGOOD clean indication that clocks and the power supplies ( etc.) are stable and within their specifications. Clean ...
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Figure 21. Noise Estimation Transition Region Datasheet ® LV Intel Pentium Microseconds ® III Processor 512K 45 ...
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LV Intel Pentium III Processor 512K 5.0 Mechanical Specifications 5.1 Surface Mount Micro-FCBGA Package The LV Intel Pentium processor 512K is available in a surface mount, 479-ball Micro-FCBGA package. III Mechanical specifications are shown in package. The Micro-FCBGA ...
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Figure 22. Micro-FCBGA Package – Top and Bottom Isometric Views LABEL TOP VIEW Datasheet LV Intel PACKAGE KEEPOUT CAPACITOR AREA DIE BOTTOM VIEW ® ® Pentium III Processor 512K 47 ...
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LV Intel Pentium III Processor 512K Figure 23. Micro-FCBGA Package – Top and Side Views 7 (K1) 8 places 5 (K) 4 places D1 NOTE: All dimensions in millimeters. Values shown are for reference 48 SUBSTRATE KEEPOUT ZONE ...
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Figure 24. Micro-FCBGA Package - Bottom View 25X 1.27 (e) NOTE: All dimensions in ...
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LV Intel Pentium III Processor 512K 5.2 Signal Listings Figure top-side view of the ball map of the LV Intel Pentium out. Table 26 lists the signals in ball number order. Figure 25. Ball Map ...
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Table 26. Table 26. Signal List by Ball Number List by Ball Number No. No. Signal Name B17 A2 NC B18 A3 A10# B19 A4 VREF B20 A5 NC B21 A6 A31# B22 A7 BR0# B23 A8 A23# B24 A9 ...
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Mechanical Specifications Table 26. Signal Table 26. List by Ball Number List by Ball Number No. Signal Name No. G24 D25# L3 G25 VSS L4 G26 D32 A12 VSS L21 H3 A8# L22 H4 VSS L23 ...
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Table 26. Signal Table 26. List by Ball Number List by Ball Number No. Signal Name No. AA6 VSS AB21 AA7 VCCCORE AB22 AA8 VSS AB23 AA9 VCCCORE AB24 AA10 VSS AB25 AA11 VCCCORE AB26 AA12 VSS AC1 AA13 VCCCORE ...
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Mechanical Specifications Table 27. Signal Listing by Signal Name No. Signal Name Signal Buffer Type K1 A3# J1 A4# G2 A5# K3 A6# J2 A7# H3 A8# G1 A9# A3 A10# J3 A11# H1 A12# D3 A13# F3 A14# G3 ...
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Table 27. Signal Listing by Signal Name No. Signal Name Signal Buffer Type R26 D44# AGTL I/O M25 D45# AGTL I/O V25 D46# AGTL I/O T24 D47# AGTL I/O M26 D48# AGTL I/O P24 D49# AGTL I/O AA26 D50# AGTL ...
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LV Intel Pentium III Processor 512K Table 28. Voltage and No-Connect Ball Locations Signal Name A2, A5, A11, B1, C1, C22, D1, D26, E1, F1, L5, N4, N24, P1, P4, P5, P26, AD4, AD13, AD23, NC AE8, AF17, ...
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Thermal Specifications and Design Considerations This section provides needed data for designing a thermal solution. The LV Intel Pentium processor 512K uses micro flip-chip ball-grid-array packaging technology and has a junction temperature (T ) specified at 100º ...
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LV Intel Pentium III Processor 512K 6.1.2 Thermal Diode The LV Intel Pentium the die temperature (T measurement kit, may monitor the die temperature of the processor for thermal management or instrumentation purposes. Note: The reading of the ...
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Processor Interface 7.1 Alphabetical Signals Reference Table 33. Signal Description (Sheet Name Type A20M# A[35:3]# I/O ADS# I/O AERR# I/O AP[1:0]# I/O BCLK/BCLK# Datasheet LV Intel If the A20M# (Address-20 Mask) input signal is asserted, the ...
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LV Intel Pentium III Processor 512K Table 33. Signal Description (Sheet Name Type BERR# I/O BINIT# I/O BNR# I/O BP[3:2]# I/O BPM[1:0]# I/O BPRI# 60 The BERR# (Bus Error) signal is asserted to indicate an ...
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Table 33. Signal Description (Sheet Name Type BR0# I/O BR1# I BSEL[1:0] O CLKREF I D[63:0]# I/O Datasheet LV Intel Description The BR0# and BR1#(Bus Request) balls drive the BREQ[1:0]# signals in the system. The BREQ[1:0]# signals ...
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LV Intel Pentium III Processor 512K Table 33. Signal Description (Sheet Name Type DBSY# I/O DEFER# DEP[7:0]# I/O DRDY# I/O FERR# FLUSH# HIT# I/O HITM# I/O IERR# IGNNE# 62 The DBSY# (Data Bus Busy) signal ...
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Table 33. Signal Description (Sheet Name Type INIT# I LINT0/INTR I LINT1/NMI LOCK# I/O NCHCTRL I PICCLK I PICD[1:0] I/O PLL1, PLL2 I PRDY# O PREQ# I Datasheet LV Intel Description The INIT# (Initialization) signal, when asserted, ...
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LV Intel Pentium III Processor 512K Table 33. Signal Description (Sheet Name Type PWRGOOD REQ[4:0]# I/O RESET# RP# I/O RS[2:0]# I/O RSP# RTTCTRL 64 The PWRGOOD (Power Good) signal is processor input. The processor requires ...
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Table 33. Signal Description (Sheet Name Type SLEWCTRL I SLP# I SMI# I STPCLK# I TCK I TDI I TDO O TESTHI[2:1] I TESTLO[2:1] I THERMDN O THERMDP I Datasheet LV Intel Description The SLEWCTRL input signal ...
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LV Intel Pentium III Processor 512K Table 33. Signal Description (Sheet Name Type THERMTRIP# TMS TRDY# I/O TRST# V CMOS_REF VID [3:0,25mV] V REF V TT_PWRGD 66 The processor protects itself from catastrophic overheating through ...
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Signal Summaries Table 34. Input Signals Name A20M# BCLK BCLK# BPRI# DEFER# FLUSH# IGNNE# INIT# INTR LINT[1:0] NCHCTRL NMI PICCLK PREQ# PWRGOOD RESET# RSP# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# TCK TDI TMS TRST# VRI# VTT_PWRGD Datasheet LV Intel Active ...
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LV Intel Pentium III Processor 512K Table 35. Output Signals Name BSEL[1:0] FERR# IERR# PRDY# TDO THERMTRIP# VID[3:0, 25mV] Table 36. Input/Output Signals (Single Driver) Name A[35:3]# ADS# AP[1:0]# BP[3:2]# BPM[1:0]# BR0# D[63:0]# DBSY# DEP[7:0]# DRDY# LOCK# REQ[4:0]# ...
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Related Documents ...................................................................................................................... 9 2 LV/ULV Intel® Pentium® III Processor 512K CPUID .................................................................15 3 System Bus Signal Groups.........................................................................................................16 4 BSEL[1:0] Encoding.................................................................................................................... Intel Pentium Processor 512K VID Values ........................................................................22 III 6 LV Intel Pentium Processor 512K Absolute Maximum ...
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Contents 2 Datasheet ...
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AGTL Bus Topology ...................................................................................................................11 2 Stop Clock State Machine ..........................................................................................................12 3 Differential/Single-Ended Clocking Example ..............................................................................15 4 Single Ended Clock BSEL Circuit (133 MHz) .............................................................................18 5 Differential Clock BSEL Circuit ...................................................................................................19 6 PLL Filter .................................................................................................................................... Power Good and ...
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Contents 2 Datasheet ...
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Introduction .................................................................................................................................... 7 1.1 Overview............................................................................................................................... 7 1.2 Terminology .......................................................................................................................... 8 1.3 Related Documents ..............................................................................................................9 2.0 Processor Features .....................................................................................................................10 2.1 512-Kbyte On-Die Integrated L2 Cache .............................................................................10 2.2 Data Prefetch Logic ............................................................................................................10 2.3 Processor System Bus and V 2.4 Differential Clocking ...
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Contents 4.3.1 PWRGOOD Signal Quality Specification............................................................... 44 4.3.2 VTT_PWRGD Signal Quality Specification............................................................ 44 5.0 Mechanical Specifications .......................................................................................................... 46 5.1 Surface Mount Micro-FCBGA Package .............................................................................. 46 5.2 Signal Listings..................................................................................................................... 50 6.0 Thermal Specifications and Design Considerations ................................................................ 57 6.1 Thermal Specifications ...