RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Processor Features

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®
®
LV Intel
Pentium
III Processor 512K
2.0

Processor Features

2.1
512-Kbyte On-Die Integrated L2 Cache
The LV Intel Pentium
L2 cache runs at the processor core speed and the increased cache size provides superior
processing power.
2.2
Data Prefetch Logic
The LV Intel Pentium
data to the L2 cache before an L1 cache request occurs. This reduces transactions between the
cache and system memory, and reduces or eliminates bus cycle penalties, which improves
performance. The processor also includes extensions to memory order and reorder buffers that
boost performance.
2.3
Processor System Bus and V
The LV Intel Pentium
Transceiver Logic (GTL) technology for the system bus. The GTL system bus operates at 1.25 V
signal levels while GTL+ operates at 1.5 V signal levels. The GTL+ signal technology is used by
®
®
the Intel
Pentium
Current P6 family processors differ from the Intel Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the LV Intel Pentium
512K are actively driven to V
times. These signals are open-drain and require termination to a supply. Because this specification
is different from the standard GTL specification, it is referred to as AGTL, or Assisted GTL in this
and other documentation related to the LV Intel Pentium
AGTL logic and AGTL+ logic are not compatible with each other due to differences with the signal
switching levels. The LV Intel Pentium
the chipset only supports the AGTL+ signal levels. For more information on AGTL or AGTL+
routing, please refer to the appropriate platform design guide.
AGTL inputs use differential receivers that require a reference voltage (V
differential receivers to determine if the input signal is a logical 0 or a logical 1. The V
typically implemented as a voltage divider on the platform. Noise decoupling is critical for the
V
signal. Refer to the platform design guide for the recommended decoupling requirements.
REF
Another important issue for the AGTL system bus is termination. System bus termination is used to
pull each signal to a high voltage level and to control reflections on the transmission line. The
processor contains on-die termination resistors that provide termination for one end of the system
bus. The other end of the system bus should also be terminated by resistors placed on the platform
or on-die termination within the agent. It is recommended that the system bus is implemented using
Dual-End Termination (DET) to meet the timings and signal integrity specified by the LV Intel
Pentium
processor 512K.
III
the LV Intel Pentium
10
processor 512K has a 512-Kbyte on-die integrated level 2 (L2) cache. The
III
processor 512K features Data Prefetch Logic that speculatively fetches
III
REF
III
processor 512K uses the original low voltage signaling of the Gunning
Pro, Intel Pentium II and Intel Pentium III processors.
for one clock cycle after the low to high transition to improve rise
TT
processor 512K cannot be installed into platforms where
III
Figure 1
is a schematic representation of the AGTL bus topology for
processor 512K; in this figure the chipset does not have on-die termination.
III
III
processor
III
processor 512K.
). V
is used by the
REF
REF
signal is
REF
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