Note: The RESET# signal requires a discrete external termination resistor on the system board.
The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL
signals are based on flight time as opposed to capacitive deratings. Analog signal simulations of the
system bus, including trace lengths, are highly recommended, especially when the recommended
layout guidelines are not followed.
Figure 1. AGTL Bus Topology
Note: R3 and R4 determine the nominal values of R1 and R2, respectively. Please refer to the LV Intel
Processor 512K Dual Processor Platform Design Guide for further dual processor
system bus layout and topology information.
The LV Intel Pentium
requires the use of two complementary clocks: BCLK and BCLK#. Benefits of differential
clocking include easier scaling to lower voltages, reduced EMI, and less jitter. The LV Intel
processor 512K also supports single-ended clocking.
Note: All references to BCLK in this document also apply to BCLK#.
Clock Control and Low Power States
The processor allows the use of AutoHALT, Stop-Grant, and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See
processor 512K supports differential clocking. Differential clocking
for a visual representation of the processor low power states.
III Processor 512K