RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 14/74:

Power and Ground Balls

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®
®
LV Intel
Pentium
III Processor 512K
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# ball specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
2.5.6
Clock Control
BCLK provides the clock signal for the processor and on-die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep state, it does not respond to interrupts or snoop transactions. During
the Sleep state, the internal clock to the L2 cache is not stopped.
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep state.
2.6

Power and Ground Balls

The operating voltage for the LV Intel Pentium
L2 cache. V
CC CORE
cache. The Voltage Regulator Module (VRM) and the Voltage Regulator are controlled by the five
voltage identification (VID) signals driven by the processor. The VID signals specify the voltage
required by the processor core. Refer to
The LV Intel Pentium
The V
inputs are used as the AGTL reference voltage for the processor. The V
REF
V) are used to provide an AGTL termination voltage to the processor. V
V
and V
CC CMOS1.8
CC CMOS2.0
for the pullup resistors that are connected to CMOS (non-AGTL) input/output signals that are
driven to/from the processor. The V
On the platform, all V
a power plane that has been divided, or it is an entire voltage plane) to minimize any voltage drop
that may occur due to trace impedance. It is also highly recommended that the platform provide
either a voltage island or a wide trace for the V
to a system ground plane. Refer to the LV Intel
Platform Design Guide for more information.
2.7
Processor System Bus Clock and Processor Clocking
The LV Intel Pentium
use either single-ended or differential signaling for the system bus and processor clocking. The
processor checks to see if the signal on ball AD1 is toggling. If this signal is toggling then the
processor operates in differential mode. Refer to
Resistor values and clock topology are listed in the appropriate platform design guide for a
differential implementation.
Note: In this document, references to BCLK also apply to its complement signal (BCLK#) in differential
implementations and when noted otherwise.
14
processor 512K is the same for the core and the
III
is defined as the power balls that supply voltage to the processor’s core and
Section 3.7
for further details on the VID voltage settings.
processor 512K has 81 V
III
CC CORE
are not voltage input balls to the processor. They are voltage sources
inputs are ground balls for the processor core and L2 cache.
SS
balls must be connected to a voltage island (an island is a portion of
CC CORE
balls. Similarly, all V
TT
®
Pentium
III
processor 512K has an auto-detect mechanism that allows the processor to
Figure 3
, 8 V
, 38 V
, and 146 V
inputs.
REF
TT
SS
inputs (1.25
TT
and
CC CMOS1.5
balls must be connected
SS
®
Processor 512K Dual Processor
III
for an example on differential clocking.
Datasheet