RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 17/74:

BSEL Encoding

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Table 3. System Bus Signal Groups (Sheet 2 of 2)
APIC Clock
APIC I/O
Thermal Diode
TAP Input
TAP Output
Power/Other
NOTES:
1. V
is the power supply for the core logic.
CCCORE
2. PLL1 and PLL2 are power/ground for the PLL analog section. See
details.
3. V
is the power supply for the system bus buffers.
TT
4. V
is the voltage reference for the AGTL input buffers.
REF
5. V
is system ground.
SS
3.1.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL signals are synchronous to BCLK (BCLK/BCLK#). All of the CMOS, Clock, APIC,
and TAP signals can be applied asynchronously to BCLK (BCLK/BCLK#). All APIC signals are
synchronous to PICCLK. All TAP signals are synchronous to TCK.
3.1.2
System Bus Frequency Select Signals
The BSEL[1:0] (Select Processor System Bus Speed) signals are used to configure the processor
for the system bus frequency. The VTT_PWRGD signal informs the processor to output the BSEL
signals. During power up the BSEL signals are indeterminate for a small period of time. If the
clock generator supports this dynamic BSEL selection, it should not sample the BSEL signals until
the VTT_PWRGD signal is asserted. The assertion of the VTT_PWRGD signal indicates that the
BSEL signals are stable and driven to a final state by the processor.
Table 4
shows the encoding scheme for BSEL[1:0]. The only supported system bus frequency for
the LV Pentium
processor 512K is 133 MHz. If another frequency is used, the processor is not
III
guaranteed to function properly.
Table 4. BSEL[1:0] Encoding
BSEL[1:0]
11
3.2
Single-Ended Clocking BSEL[1:0] Implementation
In an LV Intel Pentium
source that does not support the VTT_PWRGD protocol, the normal BSEL frequency selection
process will not work. Since the clock generator is not compatible with dynamic BSEL assertions,
all BSEL[1:0] signals should not be connected together. Instead, the BSEL pins on the clock
generator should be pulled-up to 3.3 V through a 1 K , 5% resistor. This strapping forces the clock
generator into 133 MHz clocking mode. It only supports 133 MHz capable processors.
Datasheet
LV Intel
PICCLK
PICD[1:0]
THERMDN, THERMDP
TCK, TDI, TMS, TRST#
TDO
CLKREF, VCMOS_REF, SLEWCTRL, NCHCTRL, PLL1, PLL2, RTTCTRL,
Vcc
, V
, V
, V
CORE
TT
REF
SS
System Bus Frequency
133 MHz
processor 512K platform that is using single-ended clocking or a clock
III
®
®
Pentium
III Processor 512K
“Voltage Planes” on page 21
for
17