III Processor 512K
Figure 4. Single Ended Clock BSEL Circuit (133 MHz)
Differential Host Bus Clocking Routing
LV Intel Pentium
drivers. When operating in differential clocking mode, the BCLK and BCLK#/CLKREF form a
differential pair of clock inputs. The differential pair of traces should be routed with special care
and using standard differential signaling techniques. Refer to the LV Intel
512K Dual Processor Platform Design Guide for more information.
The following sections contain the recommended topology and routing for differential clocking in
the LV Intel Pentium
Differential Clocking BSEL[1:0] Implementation
The System Bus Frequency Select Signals (BSEL[1:0]) are used to select the system bus frequency
for the host bus agents. Frequency selection is determined by the processor(s) and driven out to the
host bus clock generator. All system bus agents must operate at the same 133 MHz frequency. The
BSEL balls for the processor are open drain signals and rely on a 3.3 V pull-up resistor to set the
signal to a logic high level.
processor 512K dual-processor platforms support differential host bus clock
processor 512K dual-processor platforms.
shows the recommended implementation for a differentially