RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 19/74:

Signal State in Low-Power States

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Figure 5. Differential Clock BSEL Circuit
1K ohm
3.4

Signal State in Low-Power States

3.4.1
System Bus Signals
All of the system bus signals have AGTL input, output, or input/output drivers. The system bus
signals are tri-stated and pulled up by the termination resistors unless they are servicing snoops.
3.4.2
CMOS and Open-Drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt state these signals are allowed to toggle. These input
buffers have no internal pull-up or pull-down resistors and system logic can use CMOS or open-
drain drivers to drive them.
The open-drain output signals have open drain drivers that require external pull-up resistors. One
of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up)
when the processor is functioning normally. The FERR# output can be either tri-stated or driven to
V
when the processor is in a low-power state, depending on the condition of the floating-point
SS
unit.
3.4.3
Other Signals
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states. The APIC
clock (PICCLK) must be driven whenever BCLK and BCLK# are driven. Otherwise, it is
permitted to turn off PICCLK by holding it at V
specifications in
Table 20
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus
messages.
Datasheet
LV Intel
3.3V 3.3V
Processor 0
1K ohm
BSEL0
BSEL1
5%
5%
BSEL0
BSEL1
Processor 1
. BCLK and BCLK# must remain within the DC
SS
(for differential clocking) and
®
®
Pentium
III Processor 512K
Clock
Driver
Table 21
(for single-ended clocking).
19