Figure 5. Differential Clock BSEL Circuit
Signal State in Low-Power States
System Bus Signals
All of the system bus signals have AGTL input, output, or input/output drivers. The system bus
signals are tri-stated and pulled up by the termination resistors unless they are servicing snoops.
CMOS and Open-Drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt state these signals are allowed to toggle. These input
buffers have no internal pull-up or pull-down resistors and system logic can use CMOS or open-
drain drivers to drive them.
The open-drain output signals have open drain drivers that require external pull-up resistors. One
of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up)
when the processor is functioning normally. The FERR# output can be either tri-stated or driven to
when the processor is in a low-power state, depending on the condition of the floating-point
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states. The APIC
clock (PICCLK) must be driven whenever BCLK and BCLK# are driven. Otherwise, it is
permitted to turn off PICCLK by holding it at V
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus
. BCLK and BCLK# must remain within the DC
(for differential clocking) and
III Processor 512K
(for single-ended clocking).