RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Voltage Identification

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For additional decoupling requirements, please refer to the appropriate platform design guide for
recommended capacitor component value/quantity and placement.
3.6.3
Voltage Planes
All V
and V
CC CORE
balls must be connected to the appropriate traces on the system electronics. In addition to the main
V
, V
, and V
CC CORE
TT
PLL section. PLL1 and PLL2 should be connected according to
directly to V
.
SS
Figure 6. PLL Filter
PLL1
PLL2
3.7

Voltage Identification

There are five voltage identification (VID) balls on the LV Intel Pentium
balls can be used to support automatic selection of V
Intel Pentium
processor 512K are open drain signals versus opens or shorts. Refer to
III
level specifications for the VID signals. These pull-up resistors may be either external logic on the
motherboard or internal to the voltage regulator.
The VID signals rely on a 3.3 V pull-up resistor to set the signal to a logic high level. The VID
balls are needed to fully support voltage specification variations on current and future processors.
The voltage selection range for the processor is defined in
signal that allows the voltage regulator or voltage regulator module (VRM) to output voltage levels
in 25 mV increments. The voltage regulator or VRM must supply the voltage that is requested or
disable itself.
In addition to the new signal VID25mV, the LV Intel Pentium
signal labeled VTT_PWRGD. The VTT_PWRGD signal informs the platform that the VID and
BSEL signals are stable and should be sampled. During power-up, the VID signals will be in an
indeterminate state for a small period of time. The voltage regulator or the VRM should not latch
the VID signals until the VTT_PWRGD signal is asserted by the VRM and is sampled active. The
assertion of the VTT_PWRGD signal indicates that the VID signals are stable and are driven to the
final state by the processor. Refer to
VTT_PWRGD and the VID signals.
Datasheet
LV Intel
balls must be connected to the appropriate voltage plane. All V
SS
power supply signals, PLL1 and PLL2 provide analog decoupling to the
SS
L1
C1
CC CORE
Figure 16
for power-up timing sequence for the
®
®
Pentium
III Processor 512K
and V
TT
Figure
6. Do not connect PLL2
R1
V
V
CCT
TT
V0027-01
processor 512K. These
III
voltages. The VID balls for the LV
Table 11
Table
5. The VID25mV signal is a new
III
processor 512K has a second new
REF
for
21