RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 23/74:

Pentium Processor

Download datasheet (664Kb)Embed
PrevNext
The VID balls should be pulled up to a 3.3-V level. This may be accomplished with pull-ups
internal to the voltage regulator, which ensures valid VID pull-up voltage during power-up and
power-down sequences. When external resistors are used for the VID[3:0, 25mV] signal, the power
source must be guaranteed to be stable whenever the supply to the voltage regulator is stable. This
will prevent the possibility of the processor supply going above the specified V
of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be
accomplished by using the input voltage to the converter for the VID line pull-ups. A resistor equal
to 1 K may be used to connect the VID signals to the voltage regulator input.
Important: Intel requires that designs utilize VRM 8.5 and not IMVP-II specifications to meet the LV
Intel Pentium
processor 512K requirements.
III
To re-emphasize, VRM 8.5 introduces two new signals [VID25mV and VTT_PWRGD] that are
used by the LV Intel Pentium
balls as documented in the design guidelines (provided in the LV Intel
512K Dual Processor Platform Design Guide) will prevent the LV Intel Pentium
from operating at the specified voltage levels and core frequency.
interconnection schematic. Please refer to the VRM 8.5 DC-DC Converter Design Guideline and
the appropriate platform design guidelines for further detailed information on the voltage
identification and bus select implementation.
Refer to
Figure 16
for VID power-up sequence and timing requirements.
Figure 7. V
Power Good and Bus Select Interconnect Diagram
TT
Vtt
VRM 8.5
Voltage Regulator
VTT_PWRGD
(output)
Note: Please refer to the LV Intel
for VTT_PWRGD implementation for an LV Intel Pentium
Separate VRM 8.5 voltage regulators and processor core voltage planes are required for each
processor in a dual-processor system.
Datasheet
LV Intel
III
processor 512K and platform. Failing to connect these two new
VID[3:0,25mV]
Vtt
Vtt
R
Vcc_core
Vcc_core
VTT_PWRGD
(input)
®
®
Pentium
III
Processor 512K Dual Processor Platform Design Guide
®
®
Pentium
III Processor 512K
in the event
CC CORE
®
®
Pentium
Processor
III
III
processor 512K
Figure 7
provides a high-level
Processor
BSEL [1:0]
Clock
Driver
processor 512K platform.
III
23