The VID balls should be pulled up to a 3.3-V level. This may be accomplished with pull-ups
internal to the voltage regulator, which ensures valid VID pull-up voltage during power-up and
power-down sequences. When external resistors are used for the VID[3:0, 25mV] signal, the power
source must be guaranteed to be stable whenever the supply to the voltage regulator is stable. This
will prevent the possibility of the processor supply going above the specified V
of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be
accomplished by using the input voltage to the converter for the VID line pull-ups. A resistor equal
to 1 K may be used to connect the VID signals to the voltage regulator input.
Important: Intel requires that designs utilize VRM 8.5 and not IMVP-II specifications to meet the LV
processor 512K requirements.
To re-emphasize, VRM 8.5 introduces two new signals [VID25mV and VTT_PWRGD] that are
used by the LV Intel Pentium
balls as documented in the design guidelines (provided in the LV Intel
512K Dual Processor Platform Design Guide) will prevent the LV Intel Pentium
from operating at the specified voltage levels and core frequency.
interconnection schematic. Please refer to the VRM 8.5 DC-DC Converter Design Guideline and
the appropriate platform design guidelines for further detailed information on the voltage
identification and bus select implementation.
for VID power-up sequence and timing requirements.
Figure 7. V
Power Good and Bus Select Interconnect Diagram
Note: Please refer to the LV Intel
for VTT_PWRGD implementation for an LV Intel Pentium
Separate VRM 8.5 voltage regulators and processor core voltage planes are required for each
processor in a dual-processor system.
processor 512K and platform. Failing to connect these two new
Processor 512K Dual Processor Platform Design Guide
III Processor 512K
in the event
provides a high-level
processor 512K platform.