III Processor 512K
System Bus Clock and Processor Clocking
The BCLK and BCLK# clock inputs directly control the operating speed of the system bus
interface. All system bus timing parameters are specified with respect to the crossing point of the
rising edge of the BCLK input and the falling edge of the BCLK# input. The LV Intel Pentium
processor 512K core frequency is a multiple of the BCLK frequency. The processor core frequency
is configured during manufacturing. The configured bus ratio is visible to software in the power-on
Multiplying the bus clock frequency is necessary to increase performance while allowing for easier
distribution of signals within the system. Clock multiplication within the processor is provided by
the internal Phase Lock Loop (PLL), which requires constant frequency BCLK, BCLK# inputs.
During Reset, the PLL requires some amount of time to acquire the phase of BCLK and BCLK#.
This time is called the PLL lock latency, which is specified in
timing parameter for T18.
contains the LV Intel Pentium
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are provided in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
LV Intel Pentium
Supply Voltage with respect to V
System Bus Buffer Voltage with respect to V
System Bus Buffer DC Input Voltage with respect to V
1.25 V Buffer DC Input Voltage with respect to V
1.5 V Buffer DC Input Voltage with respect to V
1.8 V Buffer DC Input Voltage with respect to V
2.0 V Buffer DC Input Voltage with respect to V
2.5 V Buffer DC Input Voltage with respect to V
VID ball DC Input Voltage with respect to V
1. The shipping container is only rated for 65° C.
2. Parameter applies to the AGTL signal groups only. Compliance with both V
3. The voltage on the AGTL signals must never be below –0.3 or above 1.75 V with respect to ground.
4. Parameter applies to CLKREF, TESTHI, VTT_PWRGD signals.
5. Parameter applies to CMOS, Open-drain, APIC, TESTLO and TAP bus signal groups only.
6. Parameter applies to PWRGOOD signal.
7. Parameter applies to PICCLK signal.
8. Parameter applies to BCLK signal in Single-Ended Clocking Mode.
9. Parameter applies to each VID ball individually.
processor 512K stress ratings. Functional operation at the
Processor 512K Absolute Maximum Ratings
Table 17 on page
33; see the AC