RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 33/74:

APIC Bus Signal AC Specifications

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Table 17. Reset Configuration AC Specifications and Power On Timings
Symbol
Reset Configuration Signals (A[15:5]#,
T16
BR0#, FLUSH#, INIT#, PICD0) Setup
Time
Reset Configuration Signals (A[15:5]#,
T17
BR0#, FLUSH#, INIT#, PICD0) Hold Time
T18
RESET#/PWRGOOD Setup Time
T18A
V
to VTT_PWRGD Setup Time
TT
T18B
V
to PWRGOOD Setup Time
CC CORE
BSEL, VID valid time before
T18C
VTT_PWRGD assertion
T18D
RESET# inactive to Valid Outputs
T18E
RESET# inactive to Drive Signals
NOTE:
1. Applies before deassertion of RESET#
2. Applies after clock that deasserts RESET#
3. At least 1 ms must pass after PWRGOOD rises above V
specification until RESET# may be deasserted.
Table 18. APIC Bus Signal AC Specifications
Symbol
T21
PICCLK Frequency
T22
PICCLK Period
T23
PICCLK High Time
T24
PICCLK Low Time
T25
PICCLK Rise Time
T26
PICCLK Fall Time
T27
PICD[1:0] Setup Time
T28
PICD[1:0] Hold Time
PICD[1:0] Valid Delay (Rising Edge)
T29
PICD[1:0] Valid Delay (Falling Edge)
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.0 V. All CMOS signals are
referenced at 1.0 V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5 V at reset Referenced to PICCLK Rising Edge.
3. For open-drain signals, Valid Delay is synonymous with Float Delay.
4. Valid delay timings for these signals are specified into 150
system timings these specifications must be derated for external capacitance at 105 ps/pF.
5. Measured when the PICCLK signal voltage level is above 1.6 V
6. Measured when the PICCLK signal voltage level is below 1.6 V
7. Measured from 0.4 V to 1.6 V
8. Measured from 1.6 V to 0.4 V
Datasheet
LV Intel
Parameter
Min
Typ
4
2
1
1
10
1
1
4
IH18min
Parameter
Min
Max
2
33.3
30
500
10.5
10.5
0.25
0.25
8.0
2.5
1.5
1.5
12.0
to 1.5 V and 0 pF of external load. For real
®
®
Pentium
III Processor 512K
Max
Unit
Figure
Notes
BCLKs
15
1
20
BCLKs
15
2
ms
16
1, 3
ms
16
ms
16
µs
16
BCLK
15
BCLKs
15
and BCLK, BCLK# meet their AC timing
Unit
Figure
Notes
MHz
2
ns
10
ns
10
5
ns
10
6
3.0
ns
10
7
3.0
ns
10
8
ns
13
3
ns
13
3
8.7
ns
12
3,
4
1
33

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