RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Contents
4.0
System Signal Simulations......................................................................................................... 40
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality Specifications .......................................................... 40
4.2
AGTL AC Signal Quality Specifications .............................................................................. 42
4.3
Non-AGTL Signal Quality Specifications ............................................................................ 43
4.3.1
PWRGOOD Signal Quality Specification............................................................... 44
4.3.2
VTT_PWRGD Signal Quality Specification............................................................ 44
5.0
Mechanical Specifications.......................................................................................................... 46
5.1
Surface Mount Micro-FCBGA Package .............................................................................. 46
5.2
Signal Listings..................................................................................................................... 50
6.0
Thermal Specifications and Design Considerations................................................................ 57
6.1
Thermal Specifications ....................................................................................................... 57
6.1.1
THERMTRIP# Requirement .................................................................................. 57
6.1.2
Thermal Diode ....................................................................................................... 58
7.0
Processor Interface ..................................................................................................................... 59
7.1
Alphabetical Signals Reference.......................................................................................... 59
7.2
Signal Summaries............................................................................................................... 67
Figures
1
AGTL Bus Topology ................................................................................................................... 11
2
Stop Clock State Machine .......................................................................................................... 12
3
Differential/Single-Ended Clocking Example .............................................................................. 15
4
Single Ended Clock BSEL Circuit (133 MHz) ............................................................................. 18
5
Differential Clock BSEL Circuit ................................................................................................... 19
6
PLL Filter .................................................................................................................................... 21
7
V
Power Good and Bus Select Interconnect Diagram ............................................................ 23
TT
8
Power Supply Current Slew Rate (dIcc
9
Vcc
Static and Transient Tolerance ................................................................................... 27
CORE
10 BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform ...................................... 35
11 Differential BCLK/BCLK# Waveform (Common Mode) .............................................................. 35
12 BCLK/BCLK# Waveform (Differential Mode) .............................................................................. 36
13 Valid Delay Timings .................................................................................................................... 36
14 Setup and Hold Timings ............................................................................................................. 37
15 Cold/Warm Reset and Configuration Timings ............................................................................ 37
16 Power-On Sequence and Reset Timings ................................................................................... 38
17 Test Timings (Boundary Scan) ................................................................................................... 39
18 Test Reset Timings..................................................................................................................... 39
19 BCLK (Single-Ended)/PICCLK Generic Clock Waveform .......................................................... 41
20 Maximum Acceptable Overshoot/Undershoot Waveform........................................................... 42
21 Noise Estimation......................................................................................................................... 45
22 Micro-FCBGA Package – Top and Bottom Isometric Views ...................................................... 47
23 Micro-FCBGA Package – Top and Side Views .......................................................................... 48
24 Micro-FCBGA Package - Bottom View....................................................................................... 49
25 Ball Map - Top View ................................................................................................................... 50
4
/dt)......................................................................... 26
CORE
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