RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 44/74:

PWRGOOD Signal Quality Specification

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®
®
LV Intel
Pentium
III Processor 512K
4.3.1

PWRGOOD Signal Quality Specification

The processor requires PWRGOOD to be a clean indication that clocks and the power supplies
(V
, V
, etc.) are stable and within their specifications. Clean implies that the signal will
CC CORE
TT
remain below V
IL18
they come within specification. The signal will then transition monotonically to a high (1.8 V)
state.
4.3.2
VTT_PWRGD Signal Quality Specification
The VTT_PWRGD signal is an input to the processor that is used to determine that the V
is stable and that the VID and BSEL signals should be driven to their final states by the processor.
To ensure the processor correctly reads this signal, it must meet the following requirement while
the signal is in its transition region of 300 mV to 900 mV:
Amount of Noise (Glitch)
VTT_PWRGD should only enter the transition region once, after V
assertion of the signal. In addition, the VTT_PWRGD signal should have reasonable transition
time through the transition region. A sharp edge on the signal transition minimizes the chance of
noise causing a glitch on this signal. Intel recommends the following transition time for the
VTT_PWRGD signal:
Transition Time (300 mV to 900 mV)
4.3.2.1
Transition Region
The transition region covered by this requirement is 300 mV to 900 mV. Once the VTT_PWRGD
signal is in that voltage range, the processor is more sensitive to noise that may be present on the
signal. The transition region begins when the signal first crosses the 300 mV voltage level and ends
before the signal crosses 900 mV.
4.3.2.2
Transition Time
The transition time is defined as the time the signal takes to move through the transition region. A
100 µs transition time ensures that the processor receives a good transition edge.
4.3.2.3
Noise
The signal quality of the VTT_PWRGD signal is critical to the correct operation of the processor.
Every effort should be made to ensure this signal is monotonic in the transition region. If noise or
glitches are present on this signal, it must be kept to less than 100 mV of a voltage drop from the
highest voltage level received to that point. This glitch must remain less than 100 mV until the
excursion ends. The excursion ends when the voltage returns to the highest voltage previously
received.
Figure 21
44
and without errors from the time that the power supplies are turned on, until
Parameter
Parameter
provides an example graph of this situation and requirements.
power
TT
Specification
Less than 100 mV
is at nominal voltage, for the
TT
Specification
Less than or equal to 100 µs
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