RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 60/74:

Signal Description

Download datasheet (664Kb)Embed
PrevNext
®
®
LV Intel
Pentium
III Processor 512K
Table 33. Signal Description (Sheet 2 of 8)
Name
Type
BERR#
I/O
BINIT#
I/O
BNR#
I/O
BP[3:2]#
I/O
BPM[1:0]#
I/O
BPRI#
60
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents, and must connect the appropriate balls of all such agents, if used. However,
III
the LV Intel Pentium
processor 512K does not observe assertions of the BERR#
signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
• Enabled or disabled.
• Asserted optionally for internal errors along with IERR#.
• Asserted optionally by the request initiator of a bus transaction after it observes
an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents. When used, it must connect the appropriate balls of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data that is in transit is
lost. All agents reset their rotating ID for bus arbitration to the state after Reset, and
internal count information is lost. The L1 and L2 caches are not affected.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal that must connect the appropriate balls of all processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor that indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate balls of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
I
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed. It then releases the bus by deasserting BPRI#.
Description
Datasheet