RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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®
®
LV Intel
Pentium
III Processor 512K
Table 33. Signal Description (Sheet 4 of 8)
Name
Type
DBSY#
I/O
DEFER#
DEP[7:0]#
I/O
DRDY#
I/O
FERR#
FLUSH#
HIT#
I/O
HITM#
I/O
IERR#
IGNNE#
62
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate balls on all processor system bus agents.
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
I
of the addressed memory or I/O agent. This signal must connect the appropriate
balls of all processor system bus agents.
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate balls of all processor system bus agents that use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
balls of all processor system bus agents.
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
O
Intel 387 coprocessor, and is included for compatibility with systems that use
MS-DOS*-type floating-point error reporting.
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O Write instruction, it must be valid along with the TRDY# assertion of
I
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH#
to determine its power-on configuration. See the P6 Family of Processors
Hardware Developer’s Manual for details.
This signal must be connected to a 150
®
®
Intel
Pentium
III Processor 512K Dual Processor Platform Design Guide for
implementation details and resistor tolerance.
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate balls of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall; it can be continued by reasserting HIT# and HITM#
together.
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
O
transaction on the processor system bus. This transaction may be converted to an
external error signal (e.g., NMI) by system core logic. The processor keeps IERR#
asserted until the assertion of RESET#, BINIT#, or INIT#.
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and to continue to execute non-control floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
non-control floating-point instruction if a previous floating-point instruction caused
I
an error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O Write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
Description
resistor to V
. Refer to the LV
CC CMOS1.5
Datasheet