RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Table 33. Signal Description (Sheet 5 of 8)
Name
Type
INIT#
I
LINT0/INTR
I
LINT1/NMI
LOCK#
I/O
NCHCTRL
I
PICCLK
I
PICD[1:0]
I/O
PLL1, PLL2
I
PRDY#
O
PREQ#
I
Datasheet
LV Intel
Description
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector that
is configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate balls of all processor system bus agents.
When INIT# is sampled active on the active to inactive transition of RESET#, the
processor executes its Built-in Self-Test (BIST).
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate balls of
all APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable
interrupt. INTR and NMI are backward compatible with the signals of those names
®
®
on the Intel
Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space that is to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these balls as LINT[1:0] is
the default configuration.
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate balls of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus-locked
operation and ensure the atomicity of lock.
The NCHCTRL input signal provides AGTL pull-down strength control. The LV Intel
III
Pentium
processor 512K samples this input to determine the N-channel device
strength for pull-down when it is the driving agent. This signal must be connected to
a 14
resistor to V
. Refer to the LV Intel
TT
Processor Platform Design Guide for implementation details.
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC that is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus. PICD[1:0] must connect the appropriate balls of all
processors and core logic or I/O APIC components on the APIC bus.
III
The LV Intel Pentium
processor 512K has an internal analog PLL clock generator
that requires a quiet power supply. PLL1 and PLL2 are inputs to this PLL and must
be connected to V
through a low pass filter that minimizes jitter. Refer to the LV
TT
®
®
Intel
Pentium
III Processor 512K Dual Processor Platform Design Guide for
implementation details.
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
®
®
Pentium
III Processor 512K
®
®
Pentium
III Processor 512K Dual
63