RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
Page 64/74

Download datasheet (664Kb)Embed
PrevNext
®
®
LV Intel
Pentium
III Processor 512K
Table 33. Signal Description (Sheet 6 of 8)
Name
Type
PWRGOOD
REQ[4:0]#
I/O
RESET#
RP#
I/O
RS[2:0]#
I/O
RSP#
RTTCTRL
64
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (V
etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time the
power supplies are turned on until they come within specification. The signal must
then transition monotonically to a high state. PWRGOOD can be driven inactive at
I
any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in
Table
16, and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
The REQ[4:0]# (Request Command) signals must connect the appropriate balls of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after V
CLK have reached their proper specifications. Upon observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer’s Manual for details.
The processor may have its outputs tri-stated via power-on configuration.
I
Otherwise, if INIT# is sampled active during the active-to-inactive transition of
RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not
BIST is executed, the processor will begin program execution at the power on
Reset vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate balls
of all processor system bus agents.
RESET# is the only AGTL signal that does not have on-die termination. Therefore,
it is necessary to place a discrete 56
®
Pentium
III Processor 512K Dual Processor Platform Design Guide for
implementation details.
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate balls of
all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate balls of all processor system bus agents.
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate balls of all processor system bus agents.
I
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. When RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by an agent that can guarantee
correct parity.
The RTTCTRL input signal provides AGTL termination control. The LV Intel
III
Pentium
processor 512K samples this input to set the termination resistance
value for the on-die AGTL termination. This signal must be connected to a 56
I
resistor to V
on a uniprocessor platform or a 68
SS
processor platform. Refer to the LV Intel
Processor Platform Design Guide for implementation details.
Description
CC CORE
CC CORE
®
resistor to V
. Refer to the LV Intel
TT
resistor to V
on a dual-
SS
®
®
Pentium
III Processor 512K Dual
Datasheet
,
and