RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Table 33. Signal Description (Sheet 7 of 8)
Name
Type
SLEWCTRL
I
SLP#
I
SMI#
I
STPCLK#
I
TCK
I
TDI
I
TDO
O
TESTHI[2:1]
I
TESTLO[2:1]
I
THERMDN
O
THERMDP
I
Datasheet
LV Intel
Description
The SLEWCTRL input signal provides AGTL slew rate control. The LV Intel Pentium
III
processor 512K samples this input to determine the slew rate for AGTL signals
when it is the driving agent. This signal must be connected to a 110
®
®
V
. Refer to the LV Intel
Pentium
III Processor 512K Dual Processor Platform
SS
Design Guide for implementation details.
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
only recognize assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. Upon accepting a System Management Interrupt, processors save
the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input that is needed for JTAG specification support.
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output that is needed for JTAG specification support.
The TESTHI[2:1] (Test input High) signals are used during processor test and need
to be individually pulled up to V
during normal operation. Refer to the LV Intel
TT
®
Pentium
III Processor 512K Dual Processor Platform Design Guide for
implementation details.
The TESTLO[2:1] (Test input Low) signals are used during processor test and need
to be pulled to ground during normal operation. Refer to the LV Intel
Processor 512K Dual Processor Platform Design Guide for implementation details.
Thermal Diode Cathode. Used to calculate core (junction) temperature. See
Section
6.0.
Thermal Diode Anode. Used to calculate core (junction) temperature. See
6.0.
®
®
Pentium
III Processor 512K
resistor to
®
®
®
Pentium
III
Section
65