RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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1.0
Introduction .................................................................................................................................... 7
1.1
Overview............................................................................................................................... 7
1.2
Terminology .......................................................................................................................... 8
1.3
Related Documents ..............................................................................................................9
2.0
Processor Features .....................................................................................................................10
2.1
512-Kbyte On-Die Integrated L2 Cache .............................................................................10
2.2
Data Prefetch Logic ............................................................................................................10
2.3
Processor System Bus and V
2.4
Differential Clocking ............................................................................................................11
2.5
Clock Control and Low Power States .................................................................................11
2.5.1
Normal State—State 1 ...........................................................................................12
2.5.2
AutoHALT Power Down State—State 2 ................................................................12
2.5.3
Stop-Grant State—State 3 .....................................................................................13
2.5.4
HALT/Grant Snoop State—State 4 ........................................................................13
2.5.5
Sleep State—State 5 .............................................................................................13
2.5.6
Clock Control .........................................................................................................14
2.6
Power and Ground Balls .....................................................................................................14
2.7
Processor System Bus Clock and Processor Clocking ......................................................14
2.8
Processor System Bus Unused Balls .................................................................................15
2.9
LV Intel Pentium III Processor 512K CPUID.......................................................................15
3.0
Electrical Specifications .............................................................................................................16
3.1
Processor System Bus Signal Groups................................................................................16
3.1.1
Asynchronous vs. Synchronous for System Bus Signals ......................................17
3.1.2
System Bus Frequency Select Signals ..................................................................17
3.2
Single-Ended Clocking BSEL[1:0] Implementation.............................................................17
3.3
Differential Host Bus Clocking Routing ...............................................................................18
3.3.1
Differential Clocking BSEL[1:0] Implementation ....................................................18
3.4
Signal State in Low-Power States ......................................................................................19
3.4.1
System Bus Signals ...............................................................................................19
3.4.2
CMOS and Open-Drain Signals.............................................................................19
3.4.3
Other Signals .........................................................................................................19
3.5
Test Access Port (TAP) Connection ...................................................................................20
3.6
Power Supply Requirements ..............................................................................................20
3.6.1
Decoupling Guidelines ...........................................................................................20
3.6.2
Processor VCC
3.6.3
Voltage Planes.......................................................................................................21
3.7
Voltage Identification ..........................................................................................................21
3.8
System Bus Clock and Processor Clocking........................................................................24
3.9
Maximum Ratings ...............................................................................................................24
3.10
DC Specifications ...............................................................................................................25
3.11
AC Specifications................................................................................................................30
3.11.1 System Bus, Clock, APIC, TAP, CMOS, and Open-Drain AC Specifications........30
4.0
System Signal Simulations .........................................................................................................40
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality Specifications ..........................................................40
4.2
AGTL AC Signal Quality Specifications ..............................................................................42
4.3
Non-AGTL Signal Quality Specifications ............................................................................43
Datasheet
REF.............................................................................................................. 10
Decoupling ...........................................................................20
CORE
Contents
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