KM48V2104CS-6

Manufacturer Part NumberKM48V2104CS-6
Description2M x 8-Bit CMOS Dynamic RAM with Extended Data Out
ManufacturerSamsung
KM48V2104CS-6 datasheets

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KM48C2004C, KM48C2104C
KM48V2004C, KM48V2104C
2M x 8Bit CMOS Dynamic RAM with Extended Data Out
This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this
family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to real-
ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal
computer.
FEATURES
• Part Identification
- KM48C2004C/C-L (5V, 4K Ref.)
- KM48C2104C/C-L (5V, 2K Ref.)
- KM48V2004C/C-L (3.3V, 4K Ref.)
- KM48V2104C/C-L (3.3V, 2K Ref.)
• Active Power Dissipation
3.3V
Speed
4K
2K
4K
-5
324
396
495
-6
288
360
440
• Refresh Cycles
Part
Refresh
Refresh period
V
CC
NO.
cycle
Normal
C2004C
5V
4K
64ms
V2004C
3.3V
C2104C
5V
2K
32ms
V2104C
3.3V
• Performance Range
Speed
t
t
t
t
RAC
CAC
RC
HPC
-5
50ns
13ns
84ns
20ns
-6
60ns
15ns
104ns
25ns
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DESCRIPTION
• Extended Data Out Mode operation
(Fast page mode with Extended Data Out)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
Unit : mW
• JEDEC Standard pinout
5V
• Available in Plastic SOJ and TSOP(II) packages
2K
• Single +5V 10% power supply (5V product)
605
• Single +3.3V 0.3V power supply (3.3V product)
550
FUNCTIONAL BLOCK DIAGRAM
RAS
Control
L-ver
CAS
Clocks
W
128ms
Refresh Timer
Refresh Control
Refresh Counter
A0-A11
Row Address Buffer
Remark
(A0 - A10)
*1
A0 - A8
5V/3.3V
Col. Address Buffer
(A0 - A9)
*1
5V/3.3V
Note)
: 2K Refresh
*1
CMOS DRAM
Vcc
Vss
VBB Generator
Data in
Buffer
Row Decoder
Memory Array
2,097,152 x8
Cells
Data out
Column Decoder
Buffer
DQ0
to
DQ7
OE

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KM48V2104CS-6 Summary of contents

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