MC146805E2CL Motorola, MC146805E2CL Datasheet
MC146805E2CL
Related parts for MC146805E2CL
MC146805E2CL Summary of contents
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... (19) (24 (20) (23) 22 IB6 (22) 21 ]B7 Vss[ 20 (21) Pln numbers in parentheses represent suffix chip earner pins. @MOTOROLA INC., lW ..! . SUFFIX L CERAMIC PACKAGE CASE 715 S SUFFIX CEROIP PACKAGE CASE 734 P SUFFIX PLASTIC PACKAGE CASE 711 Z SUFFIX CHIP CARRIER CASE 761 ...
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M~lMUM RA~NGS (voltages referenced Ratings Supply Voltage All Input Voltages Except OSC1 Current Drain Per Pin Excluding VDD and VSS O~ating Temperature Range MCl~E2 MCl~E2C Storaga Temperature Range ~ERMAL CHARA~ERISTiCS T-I R~istance Pktic -p Ceramic ChipCa*r TIMER d POn PM ...
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DC ELECTRICAL CHARACTERISTICS @ 3.0 V Output Voltage (lLoad= 10.0 PA) Total Supply Current (CL – Loads, tcyc= 5 ps) Run (vlL=O.2 V, VIH=VDD– Wait (Test Conditions – See Note Below) Stop (Test Conditions ...
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Port A and B progra,w~~<~~nputs. vIL=O.2 V for PA@PA?z.PB@PB7, and BO-B7. VIH=VDD– O,,~V f&@~T, ~Q, and TIMER OSC1 input ~~f~,~~:prewave from VSS + 0 VDD – 0.2 V 0SC2 outpu~;ja~hncluding tester maximum, Wait rn@~t~~) IS ...
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... L 350 ,:+ ~;., ,.<<.S-.?:*, ., CMOS Equivalent MOTOROLA Semiconductor Products Inc. 5 TA=TL to TH) I v~~=5.ov * 10% fow = 5.0 MHz Typ Max Min Typ Max — — — — 2W — — lm – -,{.. :.,, , , — ...
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Nm — “ kTima < $i.$ ..../.>6 ,,,, p. eW idth Low “’k Wi+h nc .M\@ ~-’”z”’””’’””” k Transiti@ ‘k$,,, . .$” — HoI ,“’S,>,, ...
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Oscl k RESET_ J L 1920 tc,c+ toxov FIGURE 6- POWER-ON RESET AND ~~ TIMING tRL Coscl I COSC2 ‘ t> >!. Crystal Parameters Representative ...
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ASJ DS Unmux A8-A12 Address Bus Next Op Code Address +tl LASL ~ or TCR7 SP Mux BO- X’x PCL Addressl Data ~ Bus Next Op Code Rl~ ~ – The Interrupting device ...
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A OSC2* v////////////////// Unmux Op ~ode Address k A8-A12 Address 8US Mux BO- Addr;::Data 8E x Stop Op Code # g FIGURE8– INTERRUPT RECOVERY FROM STOP INSTRUCTION: tlLAsH~lg20 tcv:+ ,’~.,y ,, ...
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FUNCTIONAL PIN DESCRIPTION VDD AND Vss VDD and VSS provide power to the chip. power and VSS is ground. ~ (MASKABLE INTERRUPT REQUEST both a level-sensitive and edge-sensitive which can be used to request an interrupt M PU ...
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Oscl AS DS R/t A8-A12 BO-B7 B@B7 MPU Write FIGURE 10 – MTERNAL These eight pins interface with input/output to PA@PA7 description for details of operation. MEMORY ADDRESSING The MCl~~ is capable of addressing 8192 bytes of memory ...
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... TABLE 3 – Rl~ DDR The 1/0 pin IS [n Input o 0 Into the output Data IS written 1 o output to the 1/0 p[n The state of the 1/0 pln IS read The l/O pin output 1 1 data latch IS read MOTOROLA ( PA1 PAO ~&4 PA3 PA1 ,* ...
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Fgure are part of the external memory map. All of the ex- ternal memory space is user definable except the highest 10 locations. Locations $1 FF6 to $1 FFF of the external address space are reserved for interrupt and ...
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... These bits can be individually tested and specific action taken as a result of their state. Each of the five bits is explained below. HALF CARRY BIT (H) – The H bit is set to a one when a MOTOROLA @ FIGURE 13 – PROGRAMMING MODEL Accumulator ...
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The ~ input pin is used to reset the M PU and provide an orderly software start-up procedure. external reset mode, the = pin must stay low for a mini- mum of one tRL. The RESET pin is ...
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... FIGURE 15 – RESET AND INTERRUPT PROCESSING FLOWCHART e et l-l (in CC) 07F+SP O+DDRS CLR IRQ Logic FF+Timer + Put 1FFE on Address Bus Y m Pin = Low } Load PC from lFFE/l FFF \.\~ci’ ‘ MOTOROLA I Bit ? JClear Clear IRQ KQ Request Latch I Cycles I Semiconductor Load PC From: SWI: lFFC/l FFD 1~: ...
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VDD Interrupt Pin M~ROLA than the number of ~yc cycles it takes to execute 20 tcyc cycles. Semiconductor Ptiwb 18 the interrupt sawice routine plus Im. ...
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... Thus, all internal processing is halted MOTOROLA input which is allowed line goes to a high state, The MPU re- goes to the data input state, and the DS and AS lines go to interrupt or reset the low state (as shown lines remain at the address of the next instruction ...
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Oxillator Active Cl~r I Bit Timer Clock Active All Other Clwks stop - for @odicJj,n~~@t generation, as well as a reference in ~ency ~~,efi? measurement. The internal clock is the instructi,~ ~r6 clock and is coincident strobe. (&~:*t during ...
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... TCR4 – External enable bit: control bit used to enable the external TIMER pin (unaffected by RESET). 1 – Enable external TIMER pin, O – Disable external TIMER pin. MOTOROLA @ FIGURE 19 – TIMER BLOCK DIAGRAM Selected by TCRO, TCR1, TCR2 * Prescaler 7 Bits b - Write k Cleared bv TCR3 \ . . . ...
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... RAM and 1/0 registers and speed. + 1); PC~ Address BUSLow+ ( with extended addressing modes are arguments anywhere in memory with When using the Motorola an instruction extended addressing. The assembler mode. PC+PC+3 + 1),; Address Bus Low+( offset addressing mode, the effective is contained in the &bit index ...
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... Otherwise, ceeds to the next instruction. The span of relative addressing is limited to the range of – 126 to + 129 bytes branch instruction opcode location. The Motorola calculates the proper offset and checks to see within the span of the branch. EA=PC+2+ (PC+ 1); PC-EA if branch otherwise, PC~ BIT SET/CLEAR ...
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Op code -- .- ---- A6 lad X from Memory AE LDX 2 2 — ore A In Memorv STA – – — — — Store X in Memory STX Add Memorv to A ADD ...
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... Set Carrv Bit Clear Carry Blt Set Interrupt Mask Bit Clear Interrupt Mask Btt Software InterruDt Return from Subroutine Return from Interrupt Reset Stack Pointer No-Ooeratlon Stoo I Walt MOTOROLA @ BRANCH INSTRUCTIONS Relative Addressing Op # Mnemonic Code Bytes BRA 20 2 BRN 21 2 BHI 22 ...
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Smms Mdon coda H W Cam (From Intarrupt Mask N -i [S@n Bit) M~ROLA TABLE 9 – INSTRUCTION Sm A Tast and Sat If True. C&ti 0#~. Not Affmtad ? Ld CC Rmistw From Swk Cbrad ...
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Sk Manipulatbn Branch RFL DIR BTB BSC Hi Low m ml mlo BRSET05 BSET05 BRA NEG BTB 2 REL BRN BRCLR05 BCL~ REL 3 BTB BRSET15 BSET1 E3HI ...
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FIGURE 20 – CONNECTION TO CMOS Address R Decode (74HC13) Address A8-A12 MC1W5E2 CMOS Microprocessor 80-B7 Address/Data w AS ‘“-B7mADQ’ADQ7 “ *P Address Strobe AS Data Strobe DS Read/Wrtte R/~ m M~ROLA Semicotiuctor PERIPHERALS Chfp Enable Typical CMOS Peripheral (MC148818 ...
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... BO-B7 Address Strobe AS ~ Latch Data Strobe DS - Read/Write R/~ Interrupt m - RESET or other level on signals .,.:,.?, \ parts 4% *..{* i. .!,,.,. .! – CONNECTION<,:~~wHED NON-MULTIPLIED % AS MOTOROLA Semiconductor Products Inc. PERIPHERALS Chip Select - Ts Mm Peripherals 00-D7 RSO, ETC * ‘,! ~ :,. {,4’ CMOS ROM AND EPROM 30-07 CMOS Non- Muxed AO-A7 Memory A8 s Chip ...
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FIGURE 24 – CONNECTION MCl~5E2 CMOS Microprocessor Address/Data BO- B7 Address Strobe AS b A8-A12 FIGURE 2S – CONNECTIO~$~~$CHED St’.:+ m M~ROLA Semiconductor Ptiucb CMOS TO STATIC RAMS CMOS Static RAMs Bus DO-D7 Octal AO-A7 Latch NON-MULTIPWED CMOS RAM QO-07 ...
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... Op Code Address + Code Address 2 Op Code Address + Code Address + 1 4 Subroutine Starting Address 5 Stack Pointer 6 Stack Pointer – 1 MOTOROLA Semiconductor Products Inc Data Bua Pin Pin ,${relevant Data 1 New OD Code Op Code ...
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TABLE 11 – SUMMARY hDC EOR CPX 1 \DD LDA LDX ORA BIT 3 CMP ;BC SUB 1 2 ‘ ; ;TX 3 ...
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... BIT SBC ;TA 3TX I rsT -SL LSR I 4SR NEG 2LR ROL :OM ROR )EC INC 1 JSR — ndexed. 1&Bit Offset x Motorola reserves the right to make changes out of the application or use of anv product 11 – SUMMARY OF CYCLE-BY-CYCLE Cycle # Address Bus Code Address Code Address + 1 ...
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... If the WAIT (~ However, NOT BE circumstances; c. When mode, the vector in locations $1 FF6 and $1 FF7 (the WAIT duplimted BE improperly cumstances v~tor (following wait On future MC1-E2 necessarv. If vou have questions, distributor or Motorola Microprocessor Semicoducfor 34 (CONTINUED) Rl~ LI Data Bus Pin ~relevent ...
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... S!l:*;} .bt,, .:’ ,$ Ak. —,,~ ‘ $~ See front page for chip carrier pin assignments. m MOTOROLA PACKAGE DIMENSIONS hOTES I DIMENSION ~lSOATUM 2. POSITIONAL TO LERANCEFORLEAOS [$] O25(OO1OI ~TIA@ 3 ~ISSEATING PLANE 4 DIMENSION L’”TOCENTEROF LEADS WHEN FORMEO PARALLEL 5 DIMENSIONING ANOTOLERANCING FL PER ANSI Y145, 1913 SUFFIX ...
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T-”- / M~~LA @ .3U4 — Semiconductor Ptiwb 3W1 ED BLUESTEIN BLVD AUSTIN, TWS m- “m ,,985, ,B,m ——— _ Inc. 78721 A SUBSIDIARY OF MOTOROM INC m,e%m ...