NQ6700PXH Intel Corporation, NQ6700PXH Datasheet

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NQ6700PXH

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NQ6700PXH
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6700PXH 64-bit PCI Hub
Manufacturer
Intel Corporation
Datasheet

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Intel® 6700PXH 64-bit PCI Hub
Datasheet
July 2004
Reference Number: 302628-002

Related parts for NQ6700PXH

NQ6700PXH Summary of contents

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Intel® 6700PXH 64-bit PCI Hub Datasheet July 2004 Reference Number: 302628-002 ...

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... Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-4725 visiting Intel's website at http://www.intel.com. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2004, Intel Corporation. ...

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Contents 1 Introduction....................................................................................................................... 15 1.1 Related Documents ...........................................................................................................15 1.2 Intel® 6700PXH 64-bit PCI Hub Overview.........................................................................15 1.2.1 PCI Express* Interface (Primary Bus) .................................................................15 1.2.2 PCI/PCI-X Bus Interfaces (Secondary Bus) ........................................................16 1.2.3 PCI Standard Hot Plug Controller........................................................................16 1.2.4 I/OxAPIC Controller .............................................................................................16 1.2.5 ...

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Hot Plug Controllers .......................................................................................................... 47 2.12.1 Mode Determination ........................................................................................... 47 2.12.2 2.12.3 2.12.4 Serial Mode Operation........................................................................................ 49 2.12.4.1 Serial Input Stream............................................................................... 50 2.12.4.2 Serial Output Stream ............................................................................ 50 2.12.5 Parallel Mode Operation ..................................................................................... 51 2.12.6 2.12.6.1 Driving Bus To ...

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System Setup.....................................................................................................................70 2.17.1 Clocking...............................................................................................................70 2.17.2 Component Reset................................................................................................71 2.17.2.1 PWROK Mechanism .............................................................................72 2.17.2.2 RSTIN# Mechanism ..............................................................................72 2.17.2.3 PCI Express* Reset Mechanism ...........................................................72 2.17.2.4 Software PCI Reset (or SBR - Secondary Bus Reset)..........................73 2.17.2.5 Hot Plug Reset ......................................................................................73 2.18 Reliability, Availability, ...

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Offset 22h: ML—Memory Limit Register (D0:F0, F2) ........................... 93 3.5.1.20 Offset 24h: PMB—Prefetchable Memory Base Register 3.5.1.21 Offset 26h: PML—Prefetchable Memory Limit Register 3.5.1.22 Offset 28h: PMB_UPPER—Prefetchable Base Upper 3.5.1.23 Offset 2Ch: PML_UPPER—Prefetchable Limit Upper 3.5.1.24 Offset 30h: IOLU16—I/O ...

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Offset 6Ch: EXP_CAPSTR – PCI Express* Power 3.5.1.49 Offset 70h: EXP_PMSTSCNTL – PCI Express* Power 3.5.1.50 Offset 78h: SHPC_CAPID—SHPC Capability Identifier 3.5.1.51 Offset 79h: SHPC_NXTP—SHPC Next Item Pointer Register 3.5.1.52 Offset 7Ah: SHPC_DWSEL—SHPC DWORD Select Register 3.5.1.53 Offset 7Bh: ...

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Offset 14Ch: PX_DERRLOG – PCI-X Uncorrectable 3.6.1.15 Offset 154h: PX_MISCERRLOG – Other PCI-X 3.6.1.16 Offset 170h: PXH_STPSTS – Intel® 6700PXH 3.6.2 3.6.2.1 Offset 300h: PWR_ENH_BUDCAP – Power 3.6.2.2 Offset 304h: PWR_DATSEL – Power Budgeting Data 3.6.2.3 Offset 308h: PWR_DATREG ...

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Offset 0Fh: BIST—Built-in Self-Test Register (D0: F1, F3).................142 3.8.1.12 Offset 10h: MBAR—Memory Base Register (D0: F1, F3)...................142 3.8.1.13 Offset 2Ch: SS—Subsystem Identifier Register (D0: F1, F3) .............143 3.8.1.14 Offset 34h: CAPP—Capabilities Pointer Register (D0: F1, F3) ..........143 3.8.1.15 Offset ...

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Figures 2-1 DWord Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ................................................................................................................... 66 2-2 DWord Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ................................................................................................................... 66 2-3 DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) ................................................................................................................... 67 ...

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Tables 2-1 PCI Express* Interface Signals..........................................................................................19 2-2 PCI Bus Interface A and B Signals ....................................................................................20 2-3 PCI Bus Interface 64-bit Extension Interface A and B Signals ..........................................22 2-4 Interrupt Interface A and B Signals ....................................................................................22 2-5 General Hot Plug Interface ...

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Revision History Document Revision Number Number 302628 001 • Initial Release 302628 002 • Added Register Chapter. • Added Features list. 12 Description Date June 2004 July 2004 302628-002 ...

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Intel® 6700PXH 64-bit PCI Hub Features • PCI Express* Interface — Compatible with PCI Express Base Specification 1.0a — Compatible with PCI Express Base Specification 1.0a — Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw ...

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14 302628-002 ...

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Introduction The Intel® 6700PXH 64-bit PCI Hub is a peripheral chip that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. The Intel® 6700PXH 64-bit PCI Hub contains two PCI bus interfaces that can be ...

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Introduction 1.2.2 PCI/PCI-X Bus Interfaces (Secondary Bus) The Intel® 6700PXH 64-bit PCI Hub has two PCI Bus interfaces (PCI Bus A and PCI Bus B). In this document these buses are referred to as the secondary buses. These interfaces can ...

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JTAG The Intel® 6700PXH 64-bit PCI Hub has a JTAG (TAP) port compliant with the IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1 Specifications. The TAP controller is accessed serially through five dedicated pins. This can be ...

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Introduction 18 Intel® 6700PXH 64-bit PCI Hub Datasheet ...

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Signal Description The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal low voltage level. When “#” is not present after the signal name the ...

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Signal Description 2.2 PCI/PCI-X Bus Interface Table 2-2. PCI Bus Interface A and B Signals (Sheet Signal PA133EN PB133EN PAAD[31:0] PBAD[31:0] PACBE_[3:0]# PBCBE_[3:0]# PADEVSEL# PBDEVSEL# PAFRAME# PBFRAME# PAGNT_[5:0]# PBGNT_[5:0]# PAIRDY# PBIRDY# PAM66EN PBM66EN PAPAR PBPAR 20 Type ...

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Table 2-2. PCI Bus Interface A and B Signals (Sheet Signal PAPCIRST# PBPCIRST# PAPCIXCAP PBPCIXCAP PAPCLKI PBPCLKI PAPCLKO[6:0] PBPCLKO[6:0] PAPERR# PBPERR# PAPLOCK# PBPLOCK# PAPME# PBPME# PAREQ_[5:0]# PBREQ_[5:0]# PASERR# PBSERR# PASTOP# PBSTOP# PATRDY# PBTRDY# Intel® 6700PXH 64-bit PCI ...

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Signal Description 2.3 PCI Bus Interface 64-bit Extension There are two sets of PCI Bus extension signals; one for PCI Bus A and one for PCI Bus B. Table 2-3. PCI Bus Interface 64-bit Extension Interface A and B Signals ...

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Hot Plug Interface There are two sets of hot plug interface signals, one for PCI Bus A and one for PCI Bus B. Table 2-5. General Hot Plug Interface A and B Signals – All Hot Plug Modes Signal ...

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Signal Description Table 2-6. Serial Mode Hot Plug Signals – Interface A and B – Slots (Sheet Signal HPA_SIL# HPB_SIL# HPA_SOC HPB_SOC HPA_SOD HPB_SOD HPA_SOL HPB_SOL HPA_SOLR HPB_SOLR Table 2-7. Parallel Mode Hot Plug ...

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Table 2-7. Parallel Mode Hot Plug Signals – Interface A and B – Slots (Sheet Signal HPA_SOL/ HABUTTON2# HPB_SOL/ HBBUTTON2# HPA_SIL#/ HACLKEN_1# HPB_SIL#/ HBCLKEN_1# HPA_SOD/ HACLKEN_2 HPB_SOD/ HBCLKEN_2 PAIRQ_[11]#/ HAM66EN_1 PBIRQ_[11]#/ HBM66EN_1 PAIRQ_[12]#/ HAM66EN_2 ...

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Signal Description Table 2-7. Parallel Mode Hot Plug Signals – Interface A and B – Slots (Sheet Signal PAIRQ_[9]#/ HAPCIXCAP2_1 PBIRQ_[9]#/ HBPCIXCAP2_1 HPA_SID/ HAPCIXCAP1_2 HPB_SID/ HBPCIXCAP1_2 HPA_SOC/ HAPCIXCAP2_2 HPB_SOC/ HAPCIXCAP2_2 HPA_SLOT[1]/ HAPRSNT1_1# HPB_SLOT[1]/ HBPRSNT1_1# ...

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Table 2-7. Parallel Mode Hot Plug Signals – Interface A and B – Slots (Sheet Signal PAREQ_[4]#/ HAPRSNT2_2# PBREQ_[4]#/ HBPRSNT2_2# HAPWREN_1 HBPWREN_1 PAGNT_[3]#/ HAPWREN_2 PBGNT_[3]#/ HBPWREN_2 PAIRQ_[14]#/ HAPWRFLT_1# PBIRQ_[14]#/ HBPWRFLT_1# PAIRQ_[13]#/ HAPWRFLT_2# PBIRQ_[13]#/ HBPWRFLT_2# ...

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Signal Description 2.6 SMBus Interface Table 2-8. SMBus Interface Signals Signal SCLK SDTA SMBUS[5] SMBUS[3:1] 2.7 Miscellaneous Signals Table 2-9. Miscellaneous Signals Signal PWROK RSTIN# TCK TDI TDO TMS TRST# 28 Type I SMBus Clock. I/OD SMBus Data. I SMBus ...

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Power and Ground Table 2-10. Voltage Pins Signal RCOMP VCC VCCAEXP VCCAPCI[2:0] VCCBGEXP VCCEXP VCC15 VCC33 VREFPCI VSS VSSAEXP VSSBGEXP 2.9 Pin Straps The following signals are used for static configuration. These signals are all sampled on the rising ...

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Signal Description Table 2-11. Normal Functional Pin Straps (Sheet Strap Pin HPA_SLOT[2:0] HPB_SLOT[2:0] PA133EN PB133EN PAM66EN PBM66EN PASTRAP0 PBSTRAP0 HAATNLED_1#/ CMODE 30 Function Hot Plug Mode / # of PCI Slots: Used in conjunction with HPx_SLOT[3] signal ...

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Table 2-11. Normal Functional Pin Straps (Sheet Strap Pin SMBUS[5] SMBUS[3:1] 2.10 Signal Summary 2.10.1 Signals, Interfaces and Power Planes Table 2-12. Intel® 6700PXH 64-bit PCI Hub Signals, Interfaces and Power Planes (Sheet Intel® ...

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Signal Description Table 2-12. Intel® 6700PXH 64-bit PCI Hub Signals, Interfaces and Power Planes (Sheet Intel® 6700PXH Hot Plug Muxed 64-bit PCI Hub Signal (Parallel Signal Mode, 1-2 Slots) HPxSOD HxCLKEN_2# HPxSOL HxBUTTON2# HPxSOLR HxATNLED2# Px133EN N/A ...

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Table 2-12. Intel® 6700PXH 64-bit PCI Hub Signals, Interfaces and Power Planes (Sheet Intel® 6700PXH Hot Plug Muxed 64-bit PCI Hub Signal (Parallel Signal Mode, 1-2 Slots) PxIRQ_[2]# N/A PxIRQ_[1]# N/A PxIRQ_[0]# N/A PxM66EN N/A PxPAR N/A ...

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Signal Description Table 2-12. Intel® 6700PXH 64-bit PCI Hub Signals, Interfaces and Power Planes (Sheet Intel® 6700PXH Hot Plug Muxed 64-bit PCI Hub Signal (Parallel Signal Mode, 1-2 Slots) TDI N/A TDO N/A TMS N/A TRST# N/A ...

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Signals and Default States Table 2-14. Intel® 6700PXH 64-bit PCI Hub Signals and Default States (Sheet Signal HxATNLED_1# HxPWREN_1 HPx_PRST# HPx_RST2# HPx_SIC HPx_SID HPx_SIL# HPxSLOT[3] HPxSLOT[2] HPxSLOT[1] HPxSLOT[0] HPxSOC HPxSOD HPxSOL HPxSOLR Px133EN PxACK64# PxAD[63:0] PxCBE_[7]# ...

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Signal Description Table 2-14. Intel® 6700PXH 64-bit PCI Hub Signals and Default States (Sheet Signal PxIRDY# PxIRQ_[15]# PxIRQ_[14]# PxIRQ_[13]# PxIRQ_[12]# PxIRQ_[11]# PxIRQ_[10]# PxIRQ_[9]# PxIRQ_[8]# PxIRQ_[7]# PxIRQ_[6]# PxIRQ_[5]# PxIRQ_[4]# PxIRQ_[3]# PxIRQ_[2]# PxIRQ_[1]# PxIRQ_[0]# PxM66EN PxPAR PxPAR64 PxPCIXCAP PxPERR# ...

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Table 2-14. Intel® 6700PXH 64-bit PCI Hub Signals and Default States (Sheet Signal SMBUS[3] SMBUS[2] SMBUS[1] 2.11 PCI/PCI-X Interface 2.11.1 Initialization The Intel® 6700PXH 64-bit PCI Hub is the source bridge for the PCI bus. The Intel® ...

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Signal Description Table 2-16. PCI-X Initialization Pattern Driven by the Intel® 6700PXH 64-bit PCI Hub (Sheet PxPERR# PxDEVSEL# Deasserted Asserted Deasserted Asserted Deasserted Asserted NOTE: The Intel® 6700PXH 64-bit PCI Hub never drives these patterns on the ...

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PCI-X Transactions Table 2-18 lists the transactions supported by the Intel® 6700PXH 64-bit PCI Hub when the PCI Interface is in PCI-X mode. Table 2-18. PCI-X Transactions Supported Type of Transaction 0000 Interrupt acknowledge 0001 Special cycle 0010 I/O ...

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Signal Description the first data-phase, i.e. the Intel® 6700PXH 64-bit PCI Hub does not support PCI burst read accesses to CSR memory space. Since the CSR space is non-prefetchable, only the bytes requested within the DWord are returned. Note: Since ...

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I/O, or memory) that receive master abort termination are sent back to the PCI Express* bus or peer PCI bus with a master abort status. Delayed write requests that receive a master abort are sent back to PCI Express* ...

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Signal Description • The Configuration Lockout bit is set in the PXH_CONFIG register and the Intel® 6700PXH 64-bit PCI Hub is being configured locally after a cold boot sequence or during normal system operation. The Intel® 6700PXH 64-bit PCI Hub ...

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Type 1 configuration transaction is disconnected after the first data phase. 2.11.5.2.8 Target Termination Received by the Intel® 6700PXH 64-bit PCI Hub If the Intel® 6700PXH 64-bit PCI Hub receives a target ...

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Signal Description The Intel® 6700PXH 64-bit PCI Hub never retries a completion since it always has enough buffer space for all split requests it sends out. No transaction information is retained on any writes. The Intel® 6700PXH 64-bit PCI Hub ...

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Table 2-19. Intel® 6700PXH 64-bit PCI Hub Implementation of Requester Attribute Fields (Sheet Attribute Tag Byte Counts 2.11.6.2 4-Gbyte and 4-Kbyte Page Crossover The PCI-X bus specification allows burst transactions to cross page (in the Intel® 6700PXH ...

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Signal Description Table 2-21. Split Completion Abort Registers Index 00h Master-Abort: The Intel® 6700PXH 64-bit PCI Hub encountered a Master-Abort on the destination bus. 01h Target-Abort: The Intel® 6700PXH 64-bit PCI Hub encountered a Target-Abort on the destination bus. 2.11.7 ...

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Table 2-22. LOCK Transaction Handling End Point SHPC Memory I/OxAPIC CSR Memory PCI PCI Express* NOTES: 1. For locked reads, a response of UR-EC is reported on the PCI Express* bus. 2. The transaction is treated were ...

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Signal Description Table 2-23. Hot Plug Mode Settings HPx_SLOT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 NOTE: HPx_SLOT[2:0] are optional when Hot Plug is disabled. 2.12.2 Output Control The output interface ...

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Input Control The input interface captures eight inputs from each slot. These signals are mapped onto Intel® 6700PXH 64-bit PCI Hub pins as shown in Table 2-26 for parallel mode. • FAULT#: Over-current / Under-volt indication: When asserted, the ...

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Signal Description 2.12.4.1 Serial Input Stream The input stream shifted out by the Intel® 6700PXH 64-bit PCI Hub consists of 48 bits and is fixed. If the board implements less than 6 slots in serial mode, a bit stream value ...

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Every round of polling by the Intel® 6700PXH 64-bit PCI Hub involves shifting all 36 bits, regardless of the number of slots implemented. Bit 1 in shifted into the Intel® 6700PXH 64-bit PCI Hub in the sequence of 36 bits. ...

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Signal Description Table 2-26. Muxed Hot Plug Mode Signals Parallel Mode (Sheet Signal HxBUTTON_1# HxBUTTON_2# HxCLKEN_1# HxCLKEN_2# HxM66EN_1 HxM66EN_2 HxMRL_1# HxMRL_2# HxPCIXCAP1_1 HxPCIXCAP1_2 HxPCIXCAP2_1 HxPCIXCAP2_2 HxPRSNT1_1# HxPRSNT1_2# HxPRSNT2_1# HxPRSNT2_2# HxPWREN_1 HxPWREN_2 HxPWRFLT_1# HxPWRFLT_2# HxPWRLED_1# HxPWRLED_2# HxRST_1# HxRST_2# ...

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PxGNT_[2:0]# • PxREQ_[2:0]# • PxPERR#, PxSERR# • PxPCLKO[5:0] (Only driven to ground if enabled through the bridge – otherwise these outputs remain high. PxPCLKO[6] is not driven to ground because it is connected back to PxPCLKIN) • PxIRQ_[7:0]# • ...

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Signal Description 2.12.7 Initialization 2.12.7.1 In-box Architecture With the in-box solution it is assumed that Intel® 6700PXH 64-bit PCI Hub would be an embedded part of the system board and the system BIOS has complete knowledge of the PCI buses ...

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In each of these cases, the Intel® 6700PXH 64-bit PCI Hub will drive the PxM66EN pin to GND for the affected PCI bus. However, it should be noted that when the Intel® 6700PXH 64-bit PCI Hub is in 1-Slot mode ...

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Signal Description 2.12.11 Assumptions and Intel® 6700PXH 64-bit PCI Hub Requirements 2.12.11.1 MRL Opening during the Sequence While executing an enable or disable sequence, if the MRL of one of the cards is opened then the Intel® 6700PXH 64-bit PCI ...

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Setting the base address to a value greater than that of the limit address turns off the I/O range. When the I/O range is turned off, no I/O transactions are forwarded to the PCI bus even if the I/O enable ...

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Signal Description 2.13.2.1.16 Memory Base and Limit Address Registers The Memory Base Address and Memory Limit Address Registers define an address range that the Intel® 6700PXH 64-bit PCI Hub uses to determine when to forward memory commands. The Intel® 6700PXH ...

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Memory Accesses to I/OxAPIC and SHPC Memory Space Memory accesses to I/OxAPIC memory space are handled through two address ranges and an access enable bit in I/OxAPIC configuration space, as follows: • A 32-bit BAR (MBAR) • An alternate ...

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Signal Description Accesses to the internal Intel® 6700PXH 64-bit PCI Hub configuration registers, which includes the bridge configuration registers and the CSR memory registers, follow no ordering relationship with respect to transactions moving to and from the PCI and PCI ...

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I/OxAPIC Interrupt Controller (Functions 1 and 3) The Intel® 6700PXH 64-bit PCI Hub contains two I/OxAPIC controllers, both of which reside on the primary bus. The intended use of these controllers on the Intel® 6700PXH 64-bit PCI Hub is ...

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Signal Description signal that represents the logical OR of all of the Intel® 6700PXH 64-bit PCI Hub’s interrupt pins. The logical OR’ing includes both PCI sides A and B for the Intel® 6700PXH 64-bit PCI Hub. The DEASSERT message captures ...

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Table 2-30. System Bus Delivery Address Format (Sheet Bit Description 11:4 Enhanced Destination ID: This will be the same as bits 55:48 of the I/O Redirection Table entry for the interrupt associated with this message. 3 Redirection ...

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Signal Description Table 2-32. SMBus Address Configuration (Sheet Bit 2 1 The SMBus controller has access to all internal registers in the Intel® 6700PXH 64-bit PCI Hub. It can perform reads and writes from all registers through ...

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Table 2-33. SMBus Command Encoding (Sheet Bit 3:2 Internal Command Read DWord 01 = Write Byte 10 = Write Word 11 = Write DWord All accesses are naturally aligned to the access width. This field ...

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Signal Description 2.16.3 Configuration And Memory Reads Intel® 6700PXH 64-bit PCI Hub supports only read dword to internal register space. All Configuration and memory reads are accomplished through an SMBus write(s) and later followed by an SMBus read to read ...

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Figure 2-3. DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) S 11X0_XXX 11X0_XXX 11X0_XXX W A 11X0_XXX 11X0_XXX 11X0_XXX 11X0_XXX W A ...

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Signal Description Note: On SMBus, there is no concept of byte enables. Therefore, the Register Number written to the slave is assumed to be aligned to the length of the Internal Command. In other words, for a Write Byte internal ...

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Figure 2-10. DWord Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled) S 11X0_XXX 11X0_XXX 11X0_XXX 11X0_XXX 11X0_XXX W A 11X0_XXX 11X0_XXX W ...

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Signal Description 2.16.6 SMBus Interface Reset The master can reset the slave interface state machine in Intel® 6700PXH 64-bit PCI Hub in two ways: Τhe master holds SCL low for 25 ms cumulative. Cumulative in this case means that all ...

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Figure 2-12. Intel® 6700PXH 64-bit PCI Hub Clocking Diagram The Intel® 6700PXH 64-bit PCI Hub component uses a 100-MHz differential pair clock inputs to generate all of its core and PCI clocks. The differential clock inputs EXP_CLK and EXP_CLK# are ...

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Signal Description • PCI Express* Reset – this is message coming on the PCI Express* interface and is not a physical signal. • Software PCI Reset – this reset is initiated by writing to bridge control register of the PCI ...

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Software must choose the in-band reset time period comprehending potential mode switches that can happen on the PCI-X bus and the associated time period required to settle the voltage and meet the minimum PxPCIRST# timing requirements. This could be up ...

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Signal Description 2.18 Reliability, Availability, and Serviceability (RAS) The Intel® 6700PXH 64-bit PCI Hub provides the RAS features listed below to serve the needs of enterprise class servers and telecommunication blade applications. 2.18.1 PCI Express* Error Handling The PCI Express* ...

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PCI Express* Errors PCI Express* errors are classified as either correctable errors or uncorrectable errors. Correctable errors are those where hardware exists to correct the errors. Uncorrectable errors are errors where hardware does not exist to correct the errors. ...

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Signal Description registers are overridden with the transaction log information for the fatal error, and the fatal error is logged. However, a non-fatal error cannot override a previous fatal error. Note also that there is a single set of transaction-log ...

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The Intel® 6700PXH 64-bit PCI Hub only logs errors for cycles where it will do work. For example PCI cycle had an address parity error, and the Intel® 6700PXH 64-bit PCI Hub does not assert PxDEVSEL# for that ...

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Signal Description 78 Intel® 6700PXH 64-bit PCI Hub Datasheet ...

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Register Description The Intel® 6700PXH 64-bit PCI Hub contains registers for its PCI Express* to PCI bridge(s), Standard Hot Plug Controller, I/OxAPIC controllers, and SMBus interfaces. This chapter describes these registers. A detailed bit description is also provided. There ...

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Register Description 3.2 Memory-Mapped Registers • I/OxAPIC. In addition to the PCI Configuration Registers mentioned above, the I/OxAPIC memory-mapped registers are located in the processor memory space located by the MBAR Register (PCI offset 10h) and ABAR Register (PCI offset ...

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Symbol Description Default Value Upon a Full Reset, the Intel® 6700PXH 64-bit PCI Hub sets its internal configuration registers Upon Reset to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the ...

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Register Description Table 3-1. Configuration Register Summary (Sheet Address Offset 1E–1Fh SECSTS 20–21h MB 22–23h ML 24–25h PMB 26–27h PML 28–2Bh PB_UPPER 2C–2Fh PL_UPPER 30–31h IOLU16 32–33h IOBU16 34h CAPP 3Ch INTRL 3Dh INTRP 3E–3Fh BRIDGE_CNT 40–41h ...

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Table 3-1. Configuration Register Summary (Sheet Address Offset 5E–5Fh MSI_MC 60–67h MSI_MA 68–69h MSI_MD 6C–6Fh EXP_CAPSTR 70–73h EXP_PMSTSCNTL 78h SHPC_CAPID 79h SHPC_NXTP 7Ah SHPC_DWSEL 7Bh SHPC_STS 7C–7Fh SHPC_DWORD D8h PX_CAPID D9h PX_NXTP DA–DBh PX_SSTS DC–DFh PX_BSTS EC–EFh ...

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Register Description Table 3-1. Configuration Register Summary (Sheet Address Offset 12C–12Fh UNC_PXERRSTS 130–133h UNC_PXERRMSK 134–137h UNC_PXERRSEV 138–13Bh UNC_PXERRPTR 13C–14Bh PXTXN_HDLOG 14C–153h PX_DERRLOG 154–16Fh PX_MISCERRLOG 170–173h PXH_STPSTS 3.5.1.1 Offset 00h: VID—Vendor ID Register (D0:F0, F2) Offset: 00–01h Default ...

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Bits Type Intel® 6700PXH 64-bit PCI Hub Datasheet Reset Description 0 Interrupt Mask (INTMASK): This bit disables the ...

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Register Description 3.5.1.4 Offset 06h: STS—Status Register (D0:F0, F2) Offset: 06–07h Default Value: 0010h Bits Type 15 RWC 14 RWC 13 RWC 12 RWC 11 RWC 10 RWC Attribute: ...

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Bits Type 3 RO 2:0 RO 3.5.1.5 Offset 08h: REVID—Revision ID Register (D0:F0, F2) Offset: 08h Default Value: 00h Bits Type 7:0 RO 3.5.1.6 Offset 09h: CC—Class Code Register (D0:F0, F2) Offset: 09–0Bh Default Value: 060400h This contains the class ...

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Register Description 3.5.1.8 Offset 0Dh: MLT—Master Latency Timer Register (D0:F0, F2) Offset: 0Dh Default Value: 00h This register does not apply to the PCI Express* interface and is maintained as RW for software compatibility. Bits Type 7:3 RW 2:0 RO ...

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Offset 18h: PBN—Primary Bus Number Register (D0:F0, F2) Offset: 18h Default Value: 00h This register is used to record the bus number of the logical PCI bus segment to which the primary interface of the bridge is connected. Bits ...

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Register Description 3.5.1.14 Offset 1Bh: SLT—Secondary Latency Timer (D0:F0, F2) Offset: 1Bh Default Value: 00h (PCI) 40h (PCI-X) This timer controls the amount of time that the Intel® 6700PXH 64-bit PCI Hub will continue to burst data on its secondary ...

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Offset 1Dh: IOL—I/O Limit Register (D0:F0, F2) Offset: 1Dh Default Value: 00h This register defines the limit (aligned to a 4-Kbyte boundary) of the I/O area of the bridge. Accesses from the PCI Express* interface that are within the ...

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Register Description Bits Type 13 RWC 12 RWC 11 RWC 10 RWC 4 Reset Description 0 Received Master Abort (RMA): This bit reports the detection of a Master-Abort termination when ...

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Offset 20h: MB—Memory Base Register (D0:F0, F2) Offset: 20–21h Default Value: 0000h This register defines the base (aligned to a 1-Mbyte boundary) of the prefetchable memory area of the bridge. Accesses from the PCI Express* interface that are within ...

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Register Description Note that even though this register specifies a valid prefetchable memory window, the Intel® 6700PXH 64-bit PCI Hub never prefetches through this window in the outbound direction (reads from PCI Express* to PCI). In the inbound direction, prefetchability ...

Page 95

Offset 2Ch: PML_UPPER—Prefetchable Limit Upper 32 Bits Register (D0:F0, F2) Offset: 2C–2Fh Default Value: 00000000h This defines the upper 32 bits of the prefetchable address limit register. Bits Type 31:0 RW 3.5.1.24 Offset 30h: IOLU16—I/O Limit Upper 16 Bits ...

Page 96

Register Description 3.5.1.27 Offset 3Ch: INTRL—Interrupt Line Register (D0:F0, F2) Offset: 3Ch Default Value: 00h This register communicates interrupt line routing information. Bits Type 7:0 RW 3.5.1.28 Offset 3Dh: INTRP—Interrupt Pin Register (D0:F0, F2) Offset: 3Dh Default Value: 01h (Function ...

Page 97

Bits Type Intel® 6700PXH 64-bit PCI Hub Datasheet Reset Description 0 Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles that the Intel® 6700PXH 64-bit ...

Page 98

Register Description Bits Type Reset Description 0 VGA Enable (VGAE): Modifies the Intel® 6700PXH 64-bit PCI Hub's response to VGA compatible address Intel® 6700PXH 64-bit PCI Hub forwards the ...

Page 99

Offset 40h: CNF—Intel® 6700PXH 64-bit PCI Hub Configuration Register (D0:F0, F2) Offset: 40–41h Default Value: 0080h This register contains Intel® 6700PXH 64-bit PCI Hub specific control bits. Bits Type 15: RWS 10:9 RW ...

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Register Description Bits Type 4:0 RO 3.5.1.31 Offset 42h: MTT—Multi-Transaction Timer Register (D0:F0, F2) Offset: 42h Default Value: 00h This register controls the amount of time that the Intel® 6700PXH 64-bit PCI Hub's arbiter ...

Page 101

Offset 44h: EXP_CAPID—PCI Express* Capability Identifier Register (D0:F0, F2) Offset: 44h Default Value: 10h Bits Type 7:0 RO 3.5.1.34 Offset 45h: EXP_NXTP—PCI Express* Next Pointer Register (D0:F0, F2) Offset: 45h Default Value: 5Ch Bits Type 7:0 RO 3.5.1.35 Offset ...

Page 102

Register Description Bits Type 5 RO 4:3 RO 2:0 RO 3.5.1.37 Offset 4Ch: EXP_DEVCNTL—PCI Express* Device Control Register (D0:F0, F2) Offset: 4C – 4Dh Default Value: 0000h This register contains command bits that control the Intel® 6700PXH 64-bit PCI Hub ...

Page 103

Bits Type 3.5.1.38 Offset 4Eh: EXP_DSTS—PCI Express* Device Status Register (D0:F0, F2) Offset: 4E – 4Fh Default Value: 0000h This register contains information on the PCI Express* device status. Bits Type 15:6 ...

Page 104

Register Description 3.5.1.39 Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register (D0:F0, F2) Offset: 50 – 53h Default Value: 000B0211h This register identifies PCI Express* Link specific capabilities. Bits Type 31:18 RO 17:15 RO 14:12 RO 11:10 RO 9:4 RO 3:0 ...

Page 105

Bits Type 1:0 RW 3.5.1.41 Offset 56h: EXP_LSTS – PCI Express* Link Status Register (D0:F0, F2) Offset: 56 – 57h Default Value: 0001h (X1 link) 0041h (x4 link) 0081h (X8 link) This register provides information about PCI Express* Link specific ...

Page 106

Register Description 3.5.1.43 Offset 5Dh: MSI_NXTPTR—PCI Express* MSI Next Pointer Register (D0:F0, F2) Offset: 5Dh Default Value: 6Ch Bits Type 7:0 RO 3.5.1.44 Offset 5Eh: MSI_MCNTL—PCI Express* MSI Message Control Register (D0:F0, F2) Offset: 5E – 5Fh Default Value: 0080h ...

Page 107

Offset 64h: MSI_MUA—PCI Express* MSI Message Upper Address Register (D0:F0, F2) Offset: 64 – 67h Default Value: 00000000h Bits Type 31:2 RW 1:0 RO 3.5.1.47 Offset 68h: MSI_MD—PCI Express* MSI Message Data Register (D0:F0, F2) Offset: 68 – 69h ...

Page 108

Register Description Bits Type 15:8 RO 7:0 RO 3.5.1.49 Offset 70h: EXP_PMSTSCNTL – PCI Express* Power Management Status and Control Register (D0:F0, F2) Offset: 70– 73h Default Value: xx000000h Bits Type 31:24 RO 23: RWCS 14:13 RO 12:9 ...

Page 109

Offset 78h: SHPC_CAPID—SHPC Capability Identifier Register (D0:F0, F2) Offset: 78h Default Value: 0Ch Note: When hot plug is disabled (HPx_SLOT[3] = 0), this register is RESERVED. Bits Type 7:0 RO 3.5.1.51 Offset 79h: SHPC_NXTP—SHPC Next Item Pointer Register (D0:F0, ...

Page 110

Register Description 3.5.1.53 Offset 7Bh: SHPC_STS—SHPC Status Register (D0:F0, F2) Offset: 7Bh Default Value: x0h Note: When hot plug is disabled (HPx_SLOT[3] = 0), this register is RESERVED. Bits Type 5:0 RO 3.5.1.54 Offset 7Ch: SHPC_DWORD—SHPC ...

Page 111

Offset D9h: PX_NXTCP—PCI-X Next Capabilities Pointer Register (D0:F0, F2) Offset: D9h Default Value: 00h This register points to the next item in the Capabilities List, as required by the PCI 2.3 Specification. Bits Type 7:0 RO 3.5.1.57 Offset DAh: ...

Page 112

Register Description 3.5.1.58 Offset DCh: PX_BSTS—PCI-X Bridge Status Register (D0:F0, F2) Offset: DC – DFh Default Value: 00030000h (PCI Bus A) 00030002h (PCI Bus B, Intel® 6700PXH 64-bit PCI Hub only) Bits Type 28:22 ...

Page 113

Offset ECh: PX_ECCFA – Bridge ECC Error First Address Register (D0:F0, F2) Offset: EC – EFh Default Value: 00000000h Least significant address bits of the failing transaction. Bits Type 31:0 ROS 3.5.1.60 Offset F0h: PX_ECCSA – Bridge ECC Error ...

Page 114

Register Description 3.6 PCI Express* to PCI Bridges (D0:F0, F2) Enhanced The enhanced PCI Express* configuration access mechanism utilizes a flat memory-mapped address space to access device configuration registers. In this case, the memory address determines the configuration register accessed ...

Page 115

Bits Type 16 RWCS 15 RWCS 14 RWCS 13 RWCS 12 RWCS 11 RWCS 3 3.6.1.3 Offset 108h: ERRUNC_MSK – PCI Express* Uncorrectable Error Mask Register (D0:F0, F2) Offset: 108 – 10Bh Default Value: 00000000h ...

Page 116

Register Description Bits Type 13 RWS 12 RWS 11 RWS 3 3.6.1.4 Offset 10Ch: ERRUNC_SEV – PCI Express* Uncorrectable Error Severity Register (D0:F0, F2) Offset: 10C – 10Fh Default Value: 00030010h This register controls whether ...

Page 117

Offset 110h: ERRCOR_STS – PCI Express* Correctable Error Status Register (D0:F0, F2) Offset: 110 – 113Fh Default Value: 00000000h This register reports the error status of individual correctable error sources in the Intel® 6700PXH 64-bit PCI Hub. When an ...

Page 118

Register Description Bits Type 5 RWS 3.6.1.7 Offset 118h: ADVERR_CNTL – Advanced Error Capabilities and Control Register (D0:F0, F2) Offset: 118 – 11Bh Default Value: 00000000h The register gives the status and control for ECRC checks and also ...

Page 119

Offset 12Ch: UNC_PXERRSTS – Uncorrectable PCI/PCI-X Error Status Register (D0:F0, F2) Offset: 12C – 12Dh Default Value: 0000h This register reports error status of individual errors generated on the PCI or PCI-X secondary bus interface. An individual error status ...

Page 120

Register Description Bits Type 5 RWCS RWCS 2 RWCS 1 RWCS 0 RWCS 3.6.1.10 Offset 130h: UNC_PXERRMSK – Uncorrectable PCI/PCI-X Error Mask Register (D0:F0, F2) Offset: 130 – 133h Default Value: 000017A8h This register masks the reporting ...

Page 121

Bits Type 1 RWS 0 RWS 3.6.1.11 Offset 134h: UNC_PXERRSEV – Uncorrectable PCI/PCI-X Error Severity Register (D0:F0, F2) Offset: 134 – 135h Default Value: 2340h This register controls whether an individual PCI-X uncorrectable error is reported as a fatal or ...

Page 122

Register Description 3.6.1.12 Offset 138h: UNC_PXERRPTR – Uncorrectable PCI/PCI-X Error Pointer Register (D0:F0, F2) Offset: 138 – 13Bh Default Value: 00000000h This register points to the bit position of the first error reported in the Uncorrectable PCI/PCI-X Error Status register ...

Page 123

Offset 14Ch: PX_DERRLOG – PCI-X Uncorrectable Data Error Log Register (D0:F0, F2) Offset: 14C – 153h Default Value: 0000000000000000h This register is logged for all correctable or uncorrectable data parity errors. Bits Type 63:0 ROS 3.6.1.15 Offset 154h: PX_MISCERRLOG ...

Page 124

Register Description Bits Type 15 ROS 14 RWCS 13:11 ROS RWCS 8 ROS 7:0 ROS 124 Reset Description 0 PCI Address Low (PAL): For PCI-X requests and all PCI cycles, this bit represents the parity detected in ...

Page 125

Offset 170h: PXH_STPSTS – Intel® 6700PXH 64-bit PCI Hub Strap Status Register (D0:F0, F2) Offset: 170 – 171h Default Value: xxxxh This register indicates the status of various Power-On straps on the Intel® 6700PXH 64-bit PCI Hub. Bits Type ...

Page 126

Register Description Table 3-2. Power Management Register Summary Address Offset ...–374h PWR_BUDREG2 3.6.2.1 Offset 300h: PWR_ENH_BUDCAP – Power Budgeting Capability Header Register (D0:F0, F2) Offset: 300 – 303h Default Value: 00010004h Refer to Section 7.9.3 of the PCI Express* Base ...

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Offset 308h: PWR_DATREG – Power Budgeting Data Register (D0:F0, F2) Offset: 308 – 30Bh Default Value: 00000000h This register returns a DWORD Power Budgeting Data selected by the Data Select Register (DSEL, offset 304h). Each DWORD of the Power ...

Page 128

Register Description 3.6.2.5 Offset 314h: PWR_BUDREG0 – Power Budgeting Register 0 (D0:F0, F2) Offset: 314 – 317h Default Value: 00000000h This register reports various power consumption values in various power states. Bits Type 31:21 RO 20:0 RW 3.6.2.6 Offset 318h, ...

Page 129

Offset 36Ch–36Fh 370h–373h 3.7 Hot Plug Controller Registers The Intel® 6700PXH 64-bit PCI Hub hot plug controller allows PCI card removal, replacement and addition without powering down the system. 3.7.1 Configuration Registers Table 3-3. Hot Plug Controller Register Summary Address ...

Page 130

Register Description 3.7.1.1 Offset 00h: SHPC_BASEOFF—SHPC Base Offset Register Offset: 00–03h Default Value: 00000000h This register is used by software and/or BIOS (in conjunction with the SHPC Base Address Register, SHPC_BAR) to determine the memory base address of the SHPC ...

Page 131

Offset 10h: SBUS_CONFIG Offset: 10h Default Value: 00h This register reflects the current speed and mode of PCI bus. Bits Type 15:3: RO 2:0 RO 3.7.1.4 Offset 12h: SHPC_MSI_CNTL—SHPC MSI Control Register Offset: 12h Default Value: 00h This register ...

Page 132

Register Description 3.7.1.6 Offset 14h: CONT_COMMAND—Controller Command Register Offset: 14–15h Default Value: 0000h Bits Type 15:13 RO 12:8 RW 7:0 RW 3.7.1.7 Offset 16h: CONT_COMMAND_STS—Controller Command Status Register Offset: 16–17h Default Value: 0000h Bits Type 15 ...

Page 133

Offset 18h: INT_LOC—Interrupt Locator Register Offset: 18 – 1Bh Default Value: 00000000h Interrupt locator register for software to easily identify the source of an interrupt. Bits Type 31 3.7.1.9 Offset 1Ch: SERR_LOC—SERR Locator Register ...

Page 134

Register Description 3.7.1.10 Offset 20h: SERR_INT—Controller SERR_INT Enable Register Offset: 20–23h Default Value: 0000000Fh This register enables and disables SERR and System generation and reports global controller events. Bits Type 31: RWC 16 RWC 15 ...

Page 135

SSTS – Slot Status Field, Bits [15:0] This field contains status information about the slot. Bits Type 13:12 RO 11: 5:4 RO 3:2 RO Intel® 6700PXH ...

Page 136

Register Description Bits Type 1:0 RO 3.7.2.2 SEVL – Slot Event Latch Field, Bits [23:16] The Slot Event Latch field reports all latched events detected by the SHPC. Bits Type 23: RWC 19 RWC 18 RWC 17 RWC ...

Page 137

Bits Type 3.8 I/OxAPIC Interrupt Controller Registers (Function 1 and 3) The Intel® 6700PXH 64-bit PCI Hub contains two I/OxAPIC controllers, both of which reside on the primary bus. The intended use ...

Page 138

Register Description Address Offset 34h CAPP 40–41h ABAR 44h EXP_CAPID 45h EXP_NXTP 46–47h EXP_CAP 48–4Bh EXP_DEVCAP 4C–4Dh EXP_DEVCNTL 4E–4Fh EXP_DEVSTS 50–53h EXP_LCAP 54–55h EXP_LCNTL 56–57h EXP_LSTS 6Ch PM_CAPID 6Dh PM_NXTPTR 6E–6Fh PM_CAP 70–71h PM_CNTLSTS 80–C0h Alias of memory space registers ...

Page 139

Offset 02h: DID—Device ID Register (D0: F1, F3) Offset: 02–03h Default Value: 0326h (Function 1) 0327h (Function 3) This register contains the Device Identifiers. Bits Type 15:0 RO 3.8.1.4 Offset 04h: CMD—Command Register (D0: F1, F3) Offset: 04–05h Default ...

Page 140

Register Description Bits Type 3.8.1.5 Offset 06h: STS—Status Register (D0: F1, F3) Offset: 06–07h Default Value: 0010h Establishes the mapping between PCI 2.3 and PCI Express* for PCI 2.3 configuration space Status register. Bits Type 15 ...

Page 141

Offset 08h: REVID—Revision ID Register (D0: F1, F3) Offset: 08h Default Value: 00h Identifies the I/OxAPIC stepping of the Intel® 6700PXH 64-bit PCI Hub. Bits Type 7:0 RO 3.8.1.7 Offset 09h: CC—Class Code Register (D0: F1, F3) Offset: 09–0Bh ...

Page 142

Register Description 3.8.1.9 Offset 0Dh: MLAT—Master Latency Timer Register (D0: F1, F3) Offset: 0Dh Default Value: 00h This Master Latency Timer register does not apply to PCI Express*, and thus it is hardwired to zero by the Intel® 6700PXH 64-bit ...

Page 143

Offset 2Ch: SS—Subsystem Identifier Register (D0: F1, F3) Offset: 2C–2Fh Default Value: 00000000h This register is initialized to logic 0 by the assertion of PxPCIRST#. This register can be written only once after PxPCIRST# deassertion. Bits Type 31:16 RWOS ...

Page 144

Register Description 3.8.1.16 Offset 44h: EXP_CAPID—PCI Express* Capability Identifier Register (D0: F1, F3) Offset: 44h Default Value: 10h Bits Type 7:0 RO 3.8.1.17 Offset 45h: EXP_NXTP—PCI Express* Next Pointer Register (D0: F1, F3) Offset: 45h Default Value: 6Ch Bits Type ...

Page 145

Offset 48h: EXP_DCAP—PCI Express* Device Capability Register (D0: F1, F3) Offset: 48 – 4Bh Default Value: 00000001h This register identifies PCI Express* device specific capabilities. Bits Type 31:28 RO 27:26 RO 25:18 RO 17:12 RO 11:9 RO 8:6 RO ...

Page 146

Register Description 3.8.1.20 Offset 4Ch: DEVCNTL—Device Control Register (D0: F1, F3) Offset: 4C – 4Dh Default Value: 0020h This register controls PCI Express* device specific (Intel® 6700PXH 64-bit PCI Hub) parameters. Bits Type 15 RO 14: ...

Page 147

Offset 4Eh: DSTS—Device Status Register (D0: F1, F3) Offset: 4E-4Fh Default Value: 0000h This register provides information on specific parameters of a PCI Express* device, in this case the Intel® 6700PXH 64-bit PCI Hub. Bits Type 15 ...

Page 148

Register Description 3.8.1.22 Offset 50h: LCAP—Link Capabilities Register (D0:F1, F3) Offset: 50-53h Default Value: 0003E081h This register identifies PCI Express* link specific capabilities of the Intel® 6700PXH 64-bit PCI Hub. Bits Type 31:24 RO 23:18 RO 17:15 RO 14:12 RO ...

Page 149

Offset 54h: LCTL—Link Control Register (D0:F1, F3) Offset: 54-55h Default Value: 0000h This register controls PCI Express* link specific parameters. Bits Type 15 5 1:0 RW Intel® 6700PXH 64-bit PCI Hub ...

Page 150

Register Description 3.8.1.24 Offset 56h LSTS—Link Status Register (D0:F1, F3) Offset: 56-57h Default Value: 0001h (X1 Link) 0041h (X4 Link) 0081h (X8 Link) This register provides information about PCI Express* link specific parameters. Bits Type 15:10 RO 9:4 RO 3:0 ...

Page 151

Offset 6Eh: PM_CAP – Power Management Capabilities Register (D0: F1, F3) Offset: 6Eh Default Value: 0002h Bits Type 15:3 RO 2:0 RO 3.8.1.28 Offset 70h: PM_CNTLSTS – Power Management Control and Status Register (D0: F1, F3) Offset: 70h Default ...

Page 152

Register Description 3.8.2.2 Offset 00h: IDX—Index Register Offset: 00h Default Value: 00h The Index Register will select which indirect register appears in the window register to be manipulated by software. Software will program this register to select the desired I/OxAPIC ...

Page 153

Offset 40h: EOI—End of Interrupt (EOI) Register Offset: 40h Default Value: xxh The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is ...

Page 154

Register Description 3.8.3.2 Offset 00h: ID—APIC ID Register Offset: 00h Default Value: 00000000h The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/OxAPIC ID. This register ...

Page 155

Offset 03h: BCFG—Boot Configuration Register Offset: 03h Default Value: 00000000h The Boot Configuration contains information that is only supposed to be accessed by BIOS and is not for OS use. It contains bits that must be programmed before the ...

Page 156

Register Description Bits Type 10:8 RW 7:0 RW 3.8.3.7 Offset 11h, 13h,…, 3Fh: RDH—Redirection Table High Register Offset: 11h,13h,..,3Fh Default Value: 00000000h The information in this register is sent on the system bus to address a ...

Page 157

Component Ballout 4.1 Intel® 6700PXH 64-bit PCI Hub Ballout Figure 4-1. Intel® 6700PXH 64-bit PCI Hub Ballout (Sheet Intel® 6700PXH 64-bit PCI Hub Datasheet 157 ...

Page 158

Component Ballout Figure 4-1. Intel® 6700PXH 64-bit PCI Hub Ballout (Sheet 158 § Intel® 6700PXH 64-bit PCI Hub Datasheet ...

Page 159

Signal Lists 5.1 Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 1 of 16) Intel® 6700PXH 64-bit PCI Hub EXP_CLK_N EXP_CLK_P EXP_COMP[0] ...

Page 160

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 2 of 16) Intel® 6700PXH 64-bit PCI Hub EXP_TXP[1] EXP_TXP[2] EXP_TXP[3] EXP_TXP[4] EXP_TXP[5] EXP_TXP[6] EXP_TXP[7] HAATNLED_1_N HPA_SIC HPA_SID HPA_SIL_N HPA_SOC HPA_SOD HPA_SOL HPA_SOLR HAPWREN_1 ...

Page 161

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 3 of 16) Intel® 6700PXH 64-bit PCI Hub PAACK64_N PAAD[0] PAAD[1] PAAD[10] PAAD[11] PAAD[12] PAAD[13] PAAD[14] PAAD[15] PAAD[16] PAAD[17] PAAD[18] PAAD[19] PAAD[2] PAAD[20] PAAD[21] PAAD[22] PAAD[23] ...

Page 162

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 4 of 16) Intel® 6700PXH 64-bit PCI Hub PAAD[42] PAAD[43] PAAD[44] PAAD[45] PAAD[46] PAAD[47] PAAD[48] PAAD[49] PAAD[5] PAAD[50] PAAD[51] PAAD[52] PAAD[53] PAAD[54] PAAD[55] PAAD[56] ...

Page 163

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 5 of 16) Intel® 6700PXH 64-bit PCI Hub PAGNT_N[1] PAGNT_N[2] PAGNT_N[3] PAGNT_N[4] PAGNT_N[5] PAIRDY_N PAIRQ_N[0] PAIRQ_N[1] PAIRQ_N[10] PAIRQ_N[11] PAIRQ_N[12] PAIRQ_N[13] PAIRQ_N[14] PAIRQ_N[15] PAIRQ_N[2] PAIRQ_N[3] PAIRQ_N[4] PAIRQ_N[5] ...

Page 164

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 6 of 16) Intel® 6700PXH 64-bit PCI Hub PAREQ_N[0] PAREQ_N[1] PAREQ_N[2] PAREQ_N[3] PAREQ_N[4] PAREQ_N[5] PAREQ64_N PASERR_N PASTOP_N PASTRAP0 PATRDY_N PB133EN PBACK64_N PBAD[0] PBAD[1] PBAD[10] ...

Page 165

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 7 of 16) Intel® 6700PXH 64-bit PCI Hub PBAD[31] PBAD[32] PBAD[33] PBAD[34] PBAD[35] PBAD[36] PBAD[37] PBAD[38] PBAD[39] PBAD[4] PBAD[40] PBAD[41] PBAD[42] PBAD[43] PBAD[44] PBAD[45] PBAD[46] PBAD[47] ...

Page 166

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 8 of 16) Intel® 6700PXH 64-bit PCI Hub PBAD[9] PBCBE_N[0] PBCBE_N[1] PBCBE_N[2] PBCBE_N[3] PBCBE_N[4] PBCBE_N[5] PBCBE_N[6] PBCBE_N[7] PBDEVSEL_N PBFRAME_N PBGNT_N[0] PBGNT_N[1] PBGNT_N[2] PBGNT_N[3] PBGNT_N[4] ...

Page 167

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 9 of 16) Intel® 6700PXH 64-bit PCI Hub PBPCIXCAP PBPCLKI PBPCLKO[0] PBPCLKO[1] PBPCLKO[2] PBPCLKO[3] PBPCLKO[4] PBPCLKO[5] PBPCLKO[6] PBPERR_N PBPLOCK_N PBPME_N PBREQ_N[0] PBREQ_N[1] PBREQ_N[2] PBREQ_N[3] PBREQ_N[4] PBREQ_N[5] ...

Page 168

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 10 of 16) Intel® 6700PXH 64-bit PCI Hub SMBUS[2] SMBUS[3] SMBUS[5] TCK TDI TDO TMS TRST_N VCC VCC VCC VCC VCC VCC VCC VCC ...

Page 169

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 11 of 16) Intel® 6700PXH 64-bit PCI Hub VCC15 VCC15 VCC15 VCC15 VCC15 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 ...

Page 170

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 12 of 16) Intel® 6700PXH 64-bit PCI Hub VCCAPCI[1] VCCAPCI[2] VCCBGEXP VCCEXP VCCEXP VCCEXP VCCEXP VCCEXP VCCEXP VCCEXP VCCEXP VCCEXP VREFPCI VSS VSS VSS ...

Page 171

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 13 of 16) Intel® 6700PXH 64-bit PCI Hub VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...

Page 172

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 14 of 16) Intel® 6700PXH 64-bit PCI Hub VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...

Page 173

Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 15 of 16) Intel® 6700PXH 64-bit PCI Hub VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...

Page 174

Signal Lists Table 5-1. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Signal Name) (Sheet 16 of 16) Intel® 6700PXH 64-bit PCI Hub VSS VSS VSS VSS VSSAEXP VSSBGEXP 5.2 Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by ...

Page 175

Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 2 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 ...

Page 176

Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 3 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub C18 C19 C20 C21 C22 C23 C24 ...

Page 177

Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 4 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 ...

Page 178

Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 5 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub F22 F23 F24 G10 G11 G12 ...

Page 179

Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 6 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 ...

Page 180

Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 7 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub K10 K11 K12 K13 K14 K15 K16 K17 K18 ...

Page 181

Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 8 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub L18 L19 L20 L21 L22 L23 L24 M10 M11 ...

Page 182

Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 9 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 P1 P2 ...

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Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 10 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub R10 R11 R12 R13 R14 R15 R16 R17 R18 ...

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Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 11 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub T16 T17 T18 T19 T20 T21 T22 T23 T24 ...

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Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 12 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 ...

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Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 13 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub W20 W21 W22 W23 W24 Y10 ...

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Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 14 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AB1 AB2 ...

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Signal Lists Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 15 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub AB24 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 ...

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Table 5-2. Intel® 6700PXH 64-bit PCI Hub Signal List (Sorted by Pin Number) (Sheet 16 of 16) Pin# Intel® 6700PXH 64-bit PCI Hub AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Intel® 6700PXH 64-bit PCI Hub Datasheet Parallel HP ...

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Signal Lists 190 Intel® 6700PXH 64-bit PCI Hub Datasheet ...

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Mechanical Specifications Figure 6-1. Top View – Intel® 6700PXH 64-bit PCI Hub 567-Ball FCBGA Package Dimensions Handling Exclusion Area 0.550 in. The Intel® 6700PXH 64-bit PCI Hub is a 567-ball FCBGA package size, ...

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Mechanical Specifications Figure 6-2. Bottom View – Intel® 6700PXH 64-bit PCI Hub 567-Ball FCBGA Package Dimensions 4X 0.635 4X 15.500 23X 1.270 (0.895) 192 ...

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Figure 6-3. Side View – Intel® 6700PXH 64-bit PCI Hub 567-Ball FCBGA Package Dimensions FC BGA Substrate DIE Intel® 6700PXH 64-bit PCI Hub Datasheet H J 1.940 + 0.150 § Mechanical Specifications Detail J Scale 5:1 0.74 + 0.025 0.100 ...

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Mechanical Specifications 194 Intel® 6700PXH 64-bit PCI Hub Datasheet ...

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