PEB22504HT Infineon Technologies AG, PEB22504HT Datasheet

no-image

PEB22504HT

Manufacturer Part Number
PEB22504HT
Description
Interface, Quad Line Interface Unit
Manufacturer
Infineon Technologies AG
Datasheet
D at a S he et , DS 4, F eb ru ar y 20 01
Q ua d LI U™
Q ua d L i ne I n te r fa c e U ni t fo r
E 1 T 1 J 1
P EB 22 5 04 Ve r s i o n 1. 1
Da ta c o m
N e v e r
s t o p
t h i n k i n g .

Related parts for PEB22504HT

PEB22504HT Summary of contents

Page 1

U™ ...

Page 2

... Edition 2001-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 München, Germany © Infineon Technologies AG 2/19/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...

Page 3

U™ ...

Page 4

PEB 22504 Revision History: Previous Version: Page Subjects (major changes since last revision supply mode is not supported 7 e-mail address changed 60 Global Configuration Register 99 Power Supply Range 121 External Line Frontend Calculator 100 Transmiter output ...

Page 5

Preface The Quad Line Interface Unit PEB 22504 (QuadLIU™ flexible line interface unit for a wide area of telecommunication and data communication applications. The device contains four complete channels on one chip to save board space and power ...

Page 6

Chapter 10, Glossary • Index Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ANSI/EIA-656 ANSI T1.102 ANSI T1.231 ANSI T1.403 AT&T TR43802 AT&T TR62411 ESD Ass. Standard EOS/ESD-5.1-1993 ETSI ETS 300 011 ETSI ETS ...

Page 7

Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (QuadLIU™), device number (PEB ...

Page 8

Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

Table of Contents 4.4.6 Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

List of Tables Table 1 Control Pin Functions ...

Page 12

Overview The QuadLIU™ PEB 22504 Quad Line Interface Unit is a device to connect four E1/T1/ J1 framer devices to four analog or digital lines. The line interface is selectable for long- haul or short-haul applications and fulfills the ...

Page 13

Quad Line Interface Unit for QuadLIU™ Version 1.1 1.1 Features • High-density generic interface for all E1/T1/J1 applications • Quad analog receive and transmit circuitry for long- and short-haul applications • Clock and data recovery using an ...

Page 14

Alarm and performance monitoring per second • Two 16-bit counters for code violations and PRBS bit errors • Insertion and extraction of Alarm Indication Signals (AIS) • Elastic store for receive or transmit clock wander and jitter compensation • ...

Page 15

Logic Symbol V (1-4) DDR V (1-4) SSR RL1(1-4) RL2(1-4) V (1-4) DDX V (1-4) SSX XL1(1-4) XL2(1-4) TDI TMS TCK TRS TDO Figure 1 Logic Symbol Data Sheet RCLK(1-4) RDOP(1-4) RDON(1-4) TCLK(1-4) XDIP(1-4) XDIN/TRIST(1-4) QuadLIU PEB 22504 MFP(1-4) ...

Page 16

Typical Applications Figure 2 shows a multiple link application using the QuadLIU™. repeater application E1/T1/J1 Receive & Transmit Figure 2 QuadLIU Application Data Sheet TM QuadLIU Framer ASIC PEB 22504 Microprocessor 16 PEB 22504 QuadLIU V1.1 Overview ...

Page 17

Bidirectional Line #1 Bidirectional Line #2 Figure 3 QuadLIU Repeater Application Data Sheet RL1 RL2 XL1 XL2 1/2 TM QuadLIU RL1 RL2 XL1 XL2 17 PEB 22504 QuadLIU V1.1 Overview RDOP RCLK RDON XDIP TCLK XDIN RDOP RCLK RDON XDIP ...

Page 18

Pin Descriptions 2.1 Pin Diagram SSX TCLK4 XDIN4/TRIST4 XDIP4 TCLK3 80 XDIN3/TRIST3 XDIP3 TCLK2 XDIN2/TRIST2 XDIP2 85 TCLK1 XDIN1/TRIST1 XDIP1 INT ALE ...

Page 19

Pin Definitions and Functions Table 1 Control Pin Functions Pin No. Signal 93...99 A(0:6) 59...62 D(0:3) 65...68 D(4:7) 92 ALE Data Sheet Input (I) Function Output (O) Supply ( Address Bus ...

Page 20

Table 1 Control Pin Functions (cont’d) Pin No. Signal INT Data Sheet Input (I) Function Output (O) Supply ( WRite Enable/Read-Write Select (Intel bus mode, MODE=low) This signal indicates a write operation. When ...

Page 21

Table 1 Control Pin Functions (cont’d) Pin No. Signal 27, 33, 40, 46 MFP(1:4) LOS(1:4) ALOS(1:4) PRBSS (1:4) BPV(1:4) Data Sheet Input (I) Function Output (O) Supply (S) Multi Function Port Depending on programming of bits LIM4.PC(2:0) this multifunction port ...

Page 22

Table 1 Control Pin Functions (cont’d) Pin No. Signal 27, 33, 40, 46 XLS(1:4) (cont’d) AIS(1:4) 10 SYNC 9 FSC 87, 84, 81, 78 TRIST(1:4) Data Sheet Input (I) Function Output (O) Supply (S) O Transmit Line Status LIM4.PC(2:0) = ...

Page 23

Table 2 Signal Pin Functions Pin No. Signal 5, 21, 55, 71 RL1(1:4) ROID(1:4) 6, 20, 56, 70 RL2(1:4) 1, 25, 51, 75 XL1(1:4) XOID(1:4) 3, 23, 53, 73 XL2 (1:4) Data Sheet Input (I) Function Output (O) Supply (S) ...

Page 24

Table 2 Signal Pin Functions (cont’d) Pin No. Signal 28, 34, 41, 47 RDOP(1:4) 29, 35, 42, 48 RDON(1:4) BPV(1:4) SCLKO SCLKI Data Sheet Input (I) Function Output (O) Supply (S) O Receive Data Output/Positive Received data at RL1/2 is ...

Page 25

Table 2 Signal Pin Functions (cont’d) Pin No. Signal 88, 85, 82, 79 XDIP(1:4) 87, 84, 81, 78 XDIN(1:4) 30, 36, 43, 49 RCLK(1:4) SCLKO (1:4) Data Sheet Input (I) Function Output (O) Supply ( Transmit Data ...

Page 26

Table 2 Signal Pin Functions (cont’d) Pin No. Signal 86, 83, 80, 77 TCLK(1:4) 12 MCLK 8 RES 58 MODE Data Sheet Input (I) Function Output (O) Supply ( Transmit Clock Input of the working clock for ...

Page 27

Table 3 Power Supply Pins Pin No. Signal 4, 22, 54 DDR 7, 19, 57 SSR 2, 24, 52 DDX 26, 50, 76, V SSX 100 11, 31, 44 63, 89 13, ...

Page 28

Functional Description 3.1 Functional Overview The QuadLIU™ device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. The main interfaces are • Receive-line Interface • Transmit-line Interface • Framer interface • ...

Page 29

Block Diagram Figure 5 Block Diagram Data Sheet One of four channels 29 PEB 22504 QuadLIU V1.1 Functional Description TDO TRS TCK TMS TDI RES INT MODE ALE CS W R/RW RD/DS D(7:0) A(6:0) MFP(4:1) Common to all channels ...

Page 30

Functional Blocks 3.3.1 Microprocessor Control Unit The communication between the CPU and the QuadLIU™ is done via a set of directly accessible registers. The interface may be configured as Intel or Motorola type (by control pin MODE) with a ...

Page 31

CH4: ISR0 / ISR1 CH4: IMR0 / IMR1 CH3: ISR0 / ISR1 CH3: IMR0 / IMR1 Figure 6 Interrupt Status Registers Each interrupt indication of register ISR0 and ISR1 can be masked selectively by setting the corresponding bit in the ...

Page 32

Note: In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired, care must ...

Page 33

Boundary Scan Unit In the QuadLIU™ a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller ...

Page 34

If no boundary scan operation is used, TRS has to be connected to RST or V TCK and TDI do not need to be connected since pullup transistors ensure high input levels in this case. Test handling (boundary scan operation) ...

Page 35

Master Clocking Unit The QuadLIU™ provides a flexible clocking unit that can use a stable reference clock in the range of 1.02 MHz to 20 MHz supplied on pin MCLK. The clocking unit has to be tuned to the ...

Page 36

Interface Description 4.1 Receiver t Line Figure 9 Receiver Configuration Table 7 Examples of External Component Values (Receive) Parameter 4.1.1 Receive Line Interface Several data input ...

Page 37

Receive Equalization Network The QuadLIU™ automatically recovers the signals received on pins RL1 range -36 dB. The maximum reachable length with a 22 AWG twisted-pair cable is 6000 feet (T1/J1). After reset the QuadLIU™ ...

Page 38

Receive Clock and Data Recovery The analog received signal on port RL1/2 is equalized and then peak-detected to produce a digital signal. The receive clock and data recovery subcircuit extracts the route clock RCLK from the data stream received ...

Page 39

Pulse-Density Detector Pulse-density violations of the received signal are detected according to ANSI T1.403. Violations are indicated (LSR0.PDEN, ISR0.PDENI) if the incoming signal contains: • More than 15 consecutive zeros or • Fewer than N ones in each and ...

Page 40

ETS 300233, which requires detection intervals of at least 1 ms, can be fulfilled. • Recovery: The recovery procedure starts after detection of a logical "one" (digital receive interface pulse (analog receive interface) with ...

Page 41

The jitter attenuator works in two different modes: • Slave mode In slave mode (CMR.MAS = 0), the DCO is synchronized with the recovered route clock. In case of LOS (receive mode) or transmit clock is lost (transmit mode, bit ...

Page 42

Table 8 Clocking Modes (cont’d) Mode Internal LOS active or TCS set Slave yes Slave yes 1) The DCO can be used either in receive or transmit direction (see 2) If flexible clocking mode is selected (GCM2.VFREQ_EN = 1), the ...

Page 43

Jitter Tolerance The QuadLIU™ receiver’s tolerance to input jitter complies with ITU for CEPT applications. Figure 12 shows the curves of different input jitter specifications as well as the QuadLIU™ performance. 1000 UI 100 10 1 0.1 1 Figure ...

Page 44

Output Jitter In the absence of any input jitter, the QuadLIU™ generates the output jitter as specified in Table 9. Table 9 Output Jitter Specification Lower Cutoff AT&T TR62411 kHz 10 Hz ITU-T I.431 20 Hz ...

Page 45

Transmitter The serial bit stream is then processed by the transmitter which has the following functions: • AIS generation (Alarm Indication Signal) • Generation of AMI, B8ZS, HDB3 or CMI coded signals • Generation of IBL (In-Band Loop) code ...

Page 46

In transmit direction, only the ternary or CMI interface is supported: • Ternary signal The received data stream on pins XDIP or XDIP/N is converted into a ternary signal which is output on pins XL1 and XL2 mode ...

Page 47

Programmable Pulse Shaper and Line Build-Out In long-haul applications, the transmit pulse masks are optionally generated according to FCC68 and ANSI T1.403 for T1 applications. To reduce the crosstalk on the received signals, the QuadLIU™ can place a transmit ...

Page 48

Transmit Line Monitor The transmit line monitor compares the transmit line current on XL1 and XL2 with an on- chip transmit line current limiter. The monitor detects faults on the primary side of the transformer indicated by a highly-increased ...

Page 49

Maintenance Functions 4.4.1 Error Counter The QuadLIU™ offers two error counters. Each of them is 16 bits long. They record code violations and PRBS errors. Both error counters are buffered. Updating of the buffer is done in two modes: ...

Page 50

In-Band Loop Generation and Detection The QuadLIU™ generates an unframed IBL (In-Band Loop) pattern and detects a framed or unframed IBL pattern according to ANSI T1. 403. The detection works even in the presence of bit errors at a ...

Page 51

Remote Loop In the remote loop-back mode, the clock and data recovered from the line inputs RL1/2 or ROID are routed back to the line outputs XL1/2 or XOID via the analog or digital transmitter normal mode, ...

Page 52

Local Loop The local loop-back mode, selected by LOOP. disconnects the receive lines RL1 2 or ROID from the receiver used in analog input applications (LIM1.ECMIR = 0). Instead of the signals coming from the ...

Page 53

Digital Loop The digital loop-back mode, selected by LOOP.DLB = 1, also disconnects the receive lines RL1/2 from the receiver used in digital input applications (LIM1.ECMIR = 1). Instead of the signals coming from the line, the ...

Page 54

Alarm Simulation Alarm simulation does not affect the normal operation of the device. However, real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. The alarm ...

Page 55

Transmit Data Performance Monitoring Alternatively to the receive data performance monitoring (BPV, EXZ, LOS), this function can be switched into the transmit direction to supervise data received on pins XDIP and XDIN (LIM5.XDPM = 1). Transmit data performance (LIM2.RD(1:0) ...

Page 56

Operational Description 5.1 Operational Overview The QuadLIU™ can be operated in one of two modes, which is either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte access to all control and ...

Page 57

Table 11 Initial Values after Reset (cont’d) Register Reset Value Meaning LIM5 04 H LOOP 00 H PCD C0 H PCR 18 H LCR1 40 H LCR2 09 H LCR3 01 H XPM(2:0) 73 ,02 , IMR0, IMR1 ...

Page 58

Table 12 Initialization Parameters Basic Set Up Mode select Master clock frequency select Specification of line interface, clock generation and pulse mask Output driver enable Line interface coding Loss-of-signal detection/recovery conditions Jitter attenuation Note: Read access to unused register addresses ...

Page 59

Register Description 6.1 Control Register Addresses Table 13 Control Register Addresses Address (hexadecimal ...

Page 60

Table 13 Control Register Addresses (cont’d) Address (hexadecimal 6.2 Detailed Description of Control Registers Global Configuration Register (Read/Write) Address Value after reset GCR 0 0 ...

Page 61

FSC(1:0) FSC Source One of the four internally generated de-jittered 8-kHz clocks is output on port FSC Sourced by channel 1 (default Sourced by channel Sourced by channel Sourced by ...

Page 62

Line Interface Mode 0 (Read/Write) Addresses Value after reset LIM0 XC1 XC0 XC(1:0) Transmit Code Serial codes for transmitter and receiver can be programmed independently. The single-rail data stream ...

Page 63

EXZE Excessive Zeros Detection Enable Selects line code error detection mode. E1 mode (GCR2.PMODx = 0 Only double violations are detected Extended code violation detection: 0000 strings are detected additionally. Thereafter, incrementation of code violation counter ...

Page 64

Line Interface Mode 1 (Read/Write) Addresses Value after reset LIM1 PD EQON PD Power Down Switches the appropriate channel between power-up and power- down mode Power up ...

Page 65

ECM Error Counter Mode The function of the error counters is determined by this bit. 0 Before reading an error counter, the corresponding bit in the command register (CMDR) has to be set. The low byte of the error counter ...

Page 66

Line Interface Mode 2 (Read/Write) Addresses Value after reset LIM2 RIL2 RIL1 RIL(2:0) Receive Input Threshold Only valid if analog line interface is selected (LIM1.ECMIR = 0 ). "No ...

Page 67

RD(1:0) Select Receive Data Output These bits select the different stages of the received data path Received data is decoded (HDB3/B8ZS/AMI) and output on RDOP/ Data recovered by the DPLL (not decoded) is output on RDOP/N. ...

Page 68

EPRM Enable PRBS Monitor 0 = The PRBS monitor is disabled The PRBS monitor is enabled. XPRBS Transmit Pseudo-Random Bit Sequence (PRBS Normal transmit operation “1” in this bit position enables transmission of ...

Page 69

SCI Status Change Interrupt 0 = Interrupts are generated either at the beginning or end of the internal interrupt event The following interrupts are activated if enabled upon detection and recovering of the internal interrupt source: ISR0.LOS , ...

Page 70

Line Interface Mode 5 (Read/Write) Addresses Value after reset LIM5 ACS Automatic Clock-Switching If TCLK is missing, the transmit clock can optionally be switched to the SYNC clock automatically. ...

Page 71

LOSR(1:0) Loss-of-Signal Recovery Condition 00 = The LOS alarm is cleared if the predefined pulse-density (register PCR) is detected during the time interval which is defined by register PCD addition to the recovery condition described above a ...

Page 72

Clock Mode Register (Read/Write). Addresses Value after reset CMR DSS1 DSS0 DSS(1:0) DCO Synchronization Clock Source DCO in receive path: These bits select the reference clock source ...

Page 73

RS(1:0) Select RCLK Source These bits select the source of RCLK Extracted receive clock generated by the DPLL is used If jitter attenuation is selected in receive direction and external SCLKI is not used (LOOP.XJATT = 0, LOOP.EJATT ...

Page 74

Loop Register (Read/Write) Addresses Value after reset LOOP XJATT EJATT XJATT Jitter Attenuator Position 0 = The elastic buffer is placed in the receive path The elastic ...

Page 75

Data received on ports RL1/2 is ignored. Receiver and transmitter coding must be identical. LOSDAT Data Stream Clear in Case of LOS LOS is detected, data is processed, bit errors may occur LOS is ...

Page 76

Transmit Pulse Mask (0:2) (Read/Write) Addresses XPM0 Addresses XPM1 Addresses XPM2 Value after reset XPM0 XP12 XP11 XPM1 XP30 XP24 XPM2 XLLP XLT ...

Page 77

Example for E1 mode: 120 interface and wired as shown in XPM04 to 00: 1B XPM14 to 10: 1B XPM24 to 20: 00 XPM34 to 30: 00 Programming values for XPM(0:2): 7B Example for T1 mode The XPM values are ...

Page 78

XLLP Reserved 0 = Normal operation 1 = Reserved (not to be used) XLT Transmit Line Tristate 0 = Normal operation 1 = Transmit line XL1/XL2 is switched into high-impedance state. If this bit is set, the transmit line monitor ...

Page 79

Pulse Count Detection Register (Read/Write) Addresses Value after reset PCD PCD7 PCD(7:0) Pulse Count Detection An LOS alarm is detected if the incoming data stream has no transitions for a ...

Page 80

Loop Code Register 1 (Read/Write) Addresses Value after reset LCR1 LDCL1 LDCL0 LDCL(1:0) Length Deactivate (Down) Code These bits defines the length of the user-programmable LLB deactivate code, which is ...

Page 81

XLA Transmit LLB Activate (Up) Code 0 = Normal operation (default Normal data is replaced by the LLB activate code continuously until this bit is reset. LCR1.XLD and LIM3.XPRBS must be cleared. LLB activate code can be inserted ...

Page 82

LCR1). This generates the standard activate code "00001". Example: Transmit LLB/IBL activate Code = 00001 Register setting LCR1: xx00xx01 Register setting LCR3: xxx00001 Interrupt Mask Register (0:1) (Read/Write) Addresses IMR0: 11 ...

Page 83

Command Register (Read/Write) Addresses Value after reset CMDR RES Note: The maximum time between writing to the CMDR register and the execution of the command takes 2.5 periods of ...

Page 84

Global Clock Mode Register 1 (Read/Write) Address Value after reset GCM1 PHD_E17 PHD_E16 PHD_E15 PHD_E14 PHD_E13 PHD_E12 PHD_E11 PHD_E10 PHD_E1(0:7) Frequency Adjust for E1 For details, see Global Clock Mode Register 2 (Read/Write) Address: 3E ...

Page 85

Global Clock Mode Register 3 (Read/Write) Address Value after reset GCM3 PHD_T1 PHD_T1 7 6 PHD_T1(0:7) Frequency Adjust for T1 For details, see Global Clock Mode Register 4 (Read/Write) Address Value after reset: ...

Page 86

Global Clock Mode Register 5 (Read/Write) Address Value after reset GCM5 MCLK_ LOW MCLK_LOW Master Clock Range Low 0 = Master clock frequency divided by (PLL_M + 1) is greater than or equal to 1.5 ...

Page 87

Flexible Clock Mode Settings If flexible master clock mode is used (VFREQ_EN = 1), the according register settings can be calculated as follows (a windows-based program for automatic calculation is available, see Chapter 9.2 table below. 1. PLL_M and PLL_N ...

Page 88

Status Register Addresses Table 16 Status Register Addresses Address (hexadecimal ...

Page 89

Detailed Description of Status Registers Line Status Register 0 (Read) Addresses LOS AIS LSR0 LOS Loss-of-Signal (Red Alarm) The loss-of-signal (LOS) detection offers the flexibility to fulfill allmost all LOS ...

Page 90

T1/J1 mode: This bit is set when fewer than six zeros are detected within a time interval received on RL1/2. The bit is also set during alarm simulation, and reset if LIM0.SIM is cleared and no alarm ...

Page 91

LLBDD Line Loop-Back Deactivation Signal Detected This bit is set if the LLB deactivate signal is detected and then received over a period of more than 25 ms (E1) or 33.16 ms (T1) ,with a bit error rate less than ...

Page 92

If a short between XL1/2 is still active, outputs XL1/2 are in high-impedance state again. When the short disappears, pins XL1/2 are activated automatically and this bit is reset. With any change of this ...

Page 93

Interrupt Status Register 0 (Read) Addresses Value after reset ISR0 LLBSC XLSC PRBSSC All bits are reset when ISR0 is read. If bit LIM4.VIS is set, interrupt statuses in ...

Page 94

SLP Slip Positive The frequency of the receive route clock is less than the frequency of the receive framer interface working clock, which is a multiple of or equal to 2.048 MHz (E1) 1.544 MHz (T1/J1). Data is repeated. SLP ...

Page 95

SEC One-Second Timer The internal one-second timer has expired. The timer is derived from clock RCLK, SCLKO, SCLKI or TCLK, depending on the monitor block configuration. The selected clock source has to supply a constant clock to ensure the correct ...

Page 96

Code Violation Counter (Read) Addresses CVCL Addresses CVCH CVCL CV7 7 CVCH CV15 CV(15:0) Code Violations E1 mode: If the HDB3 or the CMI code is selected, the 16-bit counter is ...

Page 97

PRBS Bit Error Counter (Read) Addresses CVCL Addresses CVCH BECL BEC7 7 BECH BEC15 BEC(15:0) PRBS Bit Error Counter This 16-bit counter is incremented with every received PRBS bit error in ...

Page 98

Electrical Characteristics 7.1 Absolute Maximum Ratings Table 17 Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage (digital) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any pin with respect to ground ...

Page 99

Operating Range Table 18 Power Supply Range Parameter Ambient temperature Supply voltages Digital input voltages Ground 1) Voltage ripple on analog supply less than 50 mV Note: In the operating range, the functions given in the circuit description are ...

Page 100

DC Characteristics Table 19 DC Parameters Parameter Input low voltage Input high voltage Output low voltage Output high voltage Average power supply current (Analog line interface) Average power supply current (Digital line interface) Input leakage current Input leakage current ...

Page 101

Table 19 DC Parameters (cont’d) Parameter (cont’d) Differential peak voltage of a mark (between XL1 and XL2) Receiver differential peak voltage of a mark (between RL1 and RL2) Receiver input impedance Receiver sensitivity Receiver sensitivity Receiver input threshold Data Sheet ...

Page 102

Table 19 DC Parameters (cont’d) Parameter (cont’d) Loss-Of-Signal (LOS) detection limit in short- haul mode LOS detection limit in long-haul mode 1) Applies to all pins except analog pins RLx, TLx 2) Wiring conditions and external circuit configuration according to ...

Page 103

AC Characteristics 7.4.1 Master Clock Timing MCLK Figure 20 MCLK Timing Table 20 MCLK Timing Parameter Values No. Parameter 1 Clock period of MCLK 2 High phase of MCLK 3 Low phase of MCLK Clock accuracy 1) to reach ...

Page 104

JTAG Boundary Scan Interface TCK TMS TDI TDO TRS Figure 21 JTAG Boundary Scan Timing Table 21 JTAG Boundary Scan Timing Parameter Values No. Parameter 80 TCK period 81 TCK high time 82 TCK low time 83 TMS setup ...

Page 105

Reset RES Figure 22 Reset Timing Table 22 Reset Timing Parameter Values No. Parameter 1 RES pulse width low 1) while MCLK is running 7.4.4 Microprocessor Interface 7.4.4.1 Intel Bus Interface Mode Ax BHE Figure 23 ...

Page 106

Ax BHE 4 ALE Figure 24 Intel Multiplexed Address Timing Figure 25 Intel Read Cycle Timing Data Sheet 106 PEB 22504 QuadLIU V1.1 Electrical ...

Page 107

... (D15... D8) Figure 26 Intel Write Cycle Timing Table 23 Intel Bus Interface Timing Parameter Values No. Parameter 1) 1 Address setup time 2 Address hold time 3 CS setup time 3A ...

Page 108

Table 23 Intel Bus Interface Timing Parameter Values (cont’d) No. Parameter 15 Data stable before WR inactive 16 Data hold after WR inactive 1) Ax refers to address lines A(6: refers to data line D(7:0) 7.4.4.2 Motorola Bus ...

Page 109

Ax BLE D7... D0 (D15 ... D8) Figure 28 Motorola Write Cycle Timing Table 24 Motorola Bus Interface Timing Parameter Values No. Parameter 17 Address setup time before DS active 18 Address hold after DS inactive ...

Page 110

Framer Interface TCLK (TPE=0) TCLK (TPE=1) XDIP, XDIN Figure 29 TCLK Input Timing Table 25 TCLK Timing Parameter Values No. Parameter 1 TCLK period E1 (2.048 MHz) TCLK period T1/J1 (1.544 MHz) 2 TCLK high 3 TCLK low 4 ...

Page 111

RCLK (RPE=1) RCLK (RPE=0) RDOP, RDON Figure 30 RCLK Output Timing Table 26 RCLK Timing Parameter Values No. Parameter 1 RCLK period E1 (2.048 MHz) RCLK period T1/J1 (1.544 MHz) 2 RCLK high 3 RCLK low 4 RDOP, RDON setup ...

Page 112

SYNC Figure 31 SYNC Timing Table 27 SYNC Timing Parameter Values No. Parameter 1 SYNC period (SYNC = 2.048 MHz) SYNC period (SYNC = 1.544 MHz) SYNC period (SYNC = 8 kHz) 2 SYNC low time 2 SYNC low time ...

Page 113

FSC 3 RCLK Figure 32 FSC Timing Table 28 FSC Timing Parameter Values No. Parameter 1 FSC period 2 FSC low time E1 FSC low time T1/J1 3 RCLK to FSC delay E1 RCLK to FSC delay T1/J1 Data Sheet ...

Page 114

Pulse Templates - Transmitter 7.4.6.1 Pulse Template E1 V=100 % Figure 33 E1 Pulse Shape at Transmitter Output Data Sheet Electrical Characteristics 269 ns (244 + 25) 194 ns (244 - 50) 244 ns 219 ...

Page 115

Pulse Template 100 % - Figure 34 T1 Pulse Shape Table 29 T1 Pulse Template (ANSI T1.102) Maximum Curve Time [ns] 0 250 325 325 425 500 675 725 1100 1250 ...

Page 116

Capacitances Table 30 Pin Capacitances Parameter 1) Input capacitance 1) Output capacitance 1) Output capacitance 1) not tested in production 7.6 Package Characteristics Figure 35 Thermal Behaviour of Package Table 31 Package Characteristic Values Parameter 1) Thermal resistance Junction ...

Page 117

Test Configuration Test Levels Drive Levels Figure 36 Input/Output Waveforms for AC Testing Table 32 AC Test Conditions Parameter Load capacitance Input voltage high Input voltage low Test voltage high Test ...

Page 118

Package Outlines P-TQFP-100-3 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 118 PEB 22504 QuadLIU V1.1 Package Outlines ...

Page 119

Appendix 9.1 Application Notes Online access to supporting information is available on the internet page: http://www.infineon.com/falc On the same page you find as well the • Boundary Scan File for QuadLIU™ Version 1.1 (BSDL File) 9.2 Software Support The ...

Page 120

Figure 37 Master Clock Frequency Calculator Data Sheet 120 PEB 22504 QuadLIU V1.1 Appendix F0126 2001-02 ...

Page 121

Figure 38 External Line Frontend Calculator Data Sheet 121 PEB 22504 QuadLIU V1.1 Appendix F0194 2001-02 ...

Page 122

Glossary A/D Analog-to-Digital ADC Analog-to-Digital Converter AIS Alarm Indication Signal (blue alarm) AGC Automatic Gain Control ALOS Analog Loss-Of-Signal AMI Alternate Mark Inversion ANSI American National Standards Institute ATM Asynchronous Transfer Mode B8ZS Line coding to avoid too long ...

Page 123

JTAG Joined Test Action Group LBO Line Build Out LCV Line Code Violation LIU Line Interface Unit LL Local Loop LLB Line Loop Back (= IBL) LOS Loss-Of-Signal (red alarm) LSB Least Significant Bit MSB Most Significant Bit NRZ Non ...

Page 124

Index A ACS 46, 70 AIS 39, 89, 93 AISM 82 Alarm Handling 39 Alarm Simulation 54 ANSI T1.102 47 ANSI T1.231 13, 39, 71, 89, 90 ANSI T1.403 13, 39, 47, 50, 67, 89, 90 ANSI/EIA-656 119 Application Notes ...

Page 125

IBV IEEE 1149.1 14, 33 IMR0 82 IMR1 82 In-Band Loop 50 Initialization in E1 Mode 56 INT 30 Interrupt Interface 30 IPE 83 IPRBS 67 ITU-T G.703 40 ITU-T G.735 42 ITU-T G.736 13, 40 ITU-T ...

Page 126

PRBSS 89 PRBSSC 93 PRBSSCM 82 Pseudo-Random Bit Sequence 49 Pulse Density 39, 46 Pulse Shaper 47 Pulse Template 114, 115 R R1S0 60 R1S1 60 RC0 62 RC1 62 RD0 66 RD1 66 RDON0 64 RDON1 64 Read/Write Enable ...

Page 127

XLB 70 XLD 80 XLM 70 XLO 91 XLS 91 XLSC 93 XLSCM 82 XPM0 76 XPM1 76 XPM2 76 XPRBS 67 Data Sheet 127 PEB 22504 QuadLIU V1.1 2001-02 ...

Page 128

... Leistung durch umfassende Qualität zu beweisen. Wir werden Sie überzeugen Published by Infineon Technologies AG Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way ...

Related keywords