SAB-C163-L25F Infineon Technologies AG, SAB-C163-L25F Datasheet

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SAB-C163-L25F

Manufacturer Part Number
SAB-C163-L25F
Description
16-Bit MCU, CISC, C166 Family
Manufacturer
Infineon Technologies AG
Datasheet

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Data Sheet 1998-08 Preliminary

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SAB-C163-L25F Summary of contents

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Data Sheet 1998-08 Preliminary ...

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C163-L Revision History: Previous Releases: Page Subjects --- 3 V specification introduced. 2 Ordering codes removed. 3 Pin description corrected (pin 16, 17, 21, 40). 24 SSCBR removed. 26, 27 Revised description of Absolute Maximum Ratings and Operating Conditions. 36 ...

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... Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards 100-Pin TQFP Package (Thin QFP) This document describes the SAB-C163-LF, the SAB-C163-L25F and the SAF-C163-L25F. For simplicity all versions are referred to by the term C163-L throughout this document. 16 bit), 800 ns Division ( bit) ...

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Introduction The C163 derivative of the Siemens C166 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Figure 1 Logic Symbol The ...

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Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration TQFP Package (top view) P5.13/T5IN 1 P5.14/T4EUD 2 P5.15/T2EUD XTAL1 5 XTAL2 ...

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Pin Definitions and Functions Symbol Pin Input Function Numb. Out- TQFP put P5 I Port 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as timer inputs: P5. T6EUD P5.11 99 ...

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Pin Definitions and Functions (cont’d) Symbol Pin Input Function Numb. Out- TQFP put P4 IO Port 8-bit bidirectional I/O port bit-wise programmable for input or output via direction bits. For a pin configured as input, ...

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Pin Definitions and Functions (cont’d) Symbol Pin Input Function Numb. Out- TQFP put PORT0 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It P0L.0 bit-wise programmable for input or output via ...

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... EX6IN P2. EX7IN OWE 40 I Oscillator Watchdog Enable. This pin enables the PLL when high or disables it when low (e.g. to disable the OWD for testing purposes. An internal pullup device holds this input high if nothing is driving it. Note 28, - Digital Supply Voltage: DD 38, 49 during normal operation and idle mode. ...

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Functional Description The architecture of the C163-L combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the ...

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... I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C163-L is prepared to incorporate on-chip mask-programmable ROM, OTP or Flash memory for code or constant data ...

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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...

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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...

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The CPU disposes of an actual register context consisting wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be ...

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Interrupt System With an interrupt response time within a range from just 200 ns to 480 ns (in case of internal program execution), the C163-L is capable of reacting very fast to the occurence of non- deterministic events. The architecture ...

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The following table shows all of the possible C163-L interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or Request PEC Service Request Flag External Interrupt 0 CC8IR External Interrupt 1 ...

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The C163-L also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

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In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 ...

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... Parallel Ports The C163-L provides I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...

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... The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored ...

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... Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 ...

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... Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence ...

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... The following table lists all SFRs which are implemented in the C163-L in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-Peripherals (SSP) are marked with the letter “ ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address b F100 E 80 DP0L H b F102 E 81 DP0H H b F104 E 82 DP1L H b F106 E 83 DP1H H b FFC2 E1 DP2 H b ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address b FFCC FEC0 60 PECC0 H FEC2 61 PECC1 H FEC4 62 PECC2 H FEC6 63 PECC3 H FEC8 64 PECC4 H FECA 65 PECC5 H FECC ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address FE16 0B STKUN H b FF12 89 SYSCON H FE40 FF40 A0 T2CON H b FF60 B0 T2IC H FE42 FF42 A1 ...

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Absolute Maximum Ratings Parameter Storage temperature V Voltage on pins with DD respect to ground ( Voltage on any pin with V respect to ground ( ) SS Input current on any pin during overload condition Absolute ...

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... -40 85 +0.5V, except pin OWE > C163-L Unit Notes V Active mode MHz CPUmax V PowerDown mode V Active mode MHz CPUmax V Reference voltage Per pin mA °C SAB-C163-L... °C SAF-C163-L... -0.5V). The absolute sum of < 1998-08 ...

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DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, ...

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Parameter Idle mode supply current ( supply voltage) Power-down mode supply current ( supply voltage) 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output ...

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DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, ...

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Parameter Idle mode supply current ( supply voltage) Power-down mode supply current ( supply voltage) 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output ...

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Figure 7 Supply/Idle Current as a Function of Operating Frequency Semiconductor Group 11Aug98@14:48h Intermediate Version I DD3max I DD3typ I ID3max I ID3typ C163-L I DD5max I DD5typ I ID5max I ID5typ 20 ...

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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at Figure 8 Input Output Waveforms For timing purposes a ...

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AC Characteristics Definition of Internal Timing The internal operation of the C163-L is controlled by the internal CPU clock f CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations. The specification of the external timing (AC ...

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... TCL. OSC Direct Drive When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of f directly follows the frequency of f ...

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Phase Locked Loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is ...

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AC Characteristics External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol t Oscillator period OSC High time Low time 2 t Rise time 3 t Fall time 4 1) The minimum and maximum ...

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Figure 12 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables ...

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AC Characteristics Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply, t ALE cycle time = 6 TCL + 2 A Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with ...

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Parameter Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) ...

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AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply, t ALE cycle time = 6 TCL + 2 A Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with ...

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Parameter Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) ...

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ALE CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 11Aug98@14:48h Intermediate Version t 16 ...

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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 11Aug98@14:48h Intermediate Version ...

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ALE CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 11Aug98@14:48h Intermediate Version t 16 ...

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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 11Aug98@14:48h Intermediate Version ...

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AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply, t ALE cycle time = 4 TCL + 2 A Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge ...

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Parameter CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In ...

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AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply, t ALE cycle time = 4 TCL + 2 A Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge ...

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Parameter CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In ...

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ALE CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 14-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 11Aug98@14:48h ...

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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 14-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor ...

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ALE CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 14-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 11Aug98@14:48h ...

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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 14-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor ...

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AC Characteristics CLKOUT and READY (Standard Supply Voltage Range) (Operating Conditions apply, Parameter Symbol t CLKOUT cycle time t CLKOUT high time t CLKOUT low time CLKOUT rise time t t CLKOUT fall time CLKOUT rising edge to t ALE ...

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AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply, Parameter Symbol t CLKOUT cycle time t CLKOUT high time t CLKOUT low time CLKOUT rise time t t CLKOUT fall time CLKOUT rising edge to t ALE ...

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Running cycle t 32 CLKOUT ALE Command RD, WR Sync READY Async 3) READY Figure 15 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). ...

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AC Characteristics External Bus Arbitration (Standard Supply Voltage Range) (Operating Conditions apply, Parameter Symbol t HOLD input setup time to CLKOUT t CLKOUT to HLDA high or BREQ low delay t CLKOUT to HLDA low or BREQ high delay t ...

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CLKOUT t 61 HOLD HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 16 External Bus Arbitration, Releasing the Bus Notes 1) The C163-L will complete the currently running bus cycle before granting bus access. 2) This is the first ...

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CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 17 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...

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AC Characteristics Synchronous Serial Port Timing (Standard Supply Voltage Range) (Operating Conditions apply, Parameter SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE active before shift edge CE ...

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AC Characteristics Synchronous Serial Port Timing (Reduced Supply Voltage Range) (Operating Conditions apply, Parameter SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE active before shift edge CE ...

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... The bit timing is repeated for all bits to be transmitted or received. 3) The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active. Semiconductor Group ...

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Package Outlines Plastic Package, P-TQFP-100-3 (SMD) (Plastic Thin Metric Quad Flat Package) Figure 20 Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 11Aug98@14:48h Intermediate ...

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Semiconductor Group 11Aug98@14:48h Intermediate Version 65 C163-L 1998-08 ...

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Siemens Aktiengesellschaft Published by Semiconductor Group 11Aug98@14:48h Intermediate Version 66 C163-L 1998-08 ...

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