UPD78F9026AGB-8ES NEC, UPD78F9026AGB-8ES Datasheet

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UPD78F9026AGB-8ES

Manufacturer Part Number
UPD78F9026AGB-8ES
Description
8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet

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µ µ µ µ PD789026 Subseries
8-Bit Single-Chip Microcontrollers
User’s Manual
µ µ µ µ PD789022
µ µ µ µ PD789024
µ µ µ µ PD789025
µ µ µ µ PD789026
µ µ µ µ PD78F9026A
Document No.
Date Published February 2003 N CP(K)
Printed in Japan
©
U11919EJ4V0UD00 (4th edition)

Related parts for UPD78F9026AGB-8ES

UPD78F9026AGB-8ES Summary of contents

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User’s Manual µ µ µ µ PD789026 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789022 µ µ µ µ PD789024 µ µ µ µ PD789025 µ µ µ µ PD789026 µ µ µ µ PD78F9026A Document No. U11919EJ4V0UD00 (4th ...

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User’s Manual U11919EJ4V0UD ...

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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...

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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...

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Page Deletion of the following packages Throughout • 42-pin plastic shrink DIP (CU type) • 44-pin plastic QFP (GB-3BS-MTX type) p.33 Modification of pin handling of V pp.92, 94 Modification of description in 6.4.1 Operation as timer interrupt and 6.4.2 ...

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Readers This manual is intended for user engineers who wish to understand the functions of the µ PD789026 Subseries to design and develop its application systems and programs. The target subseries is the µ PD789026 Subseries, which consists of the ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD789026 Subseries User’s Manual 78K/0S Series Instructions User’s Manual Documents Related to Development Software ...

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... SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...

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... V ............................................................................................................................................... µ PD78F9026A only) ............................................................................................................ 33 2.2. 2.2.13 IC (mask ROM version only) ....................................................................................................... 33 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .........................................34 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................36 3.1 Memory Space ............................................................................................................................36 3.1.1 Internal program memory space ................................................................................................. 41 3.1.2 Internal data memory (internal high-speed RAM) space............................................................. 42 3.1.3 Special function register (SFR) area ........................................................................................... 42 3.1.4 Data memory addressing ............................................................................................................ 43 3 ...

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... Function of Clock Generator.....................................................................................................79 5.2 Configuration of Clock Generator ............................................................................................79 5.3 Register Controlling Clock Generator......................................................................................80 5.4 System Clock Oscillator ............................................................................................................81 5.4.1 System clock oscillator ................................................................................................................81 5.4.2 Examples of incorrect resonator connection ...............................................................................82 5.4.3 Divider circuit...............................................................................................................................83 5.5 Operation of Clock Generator ...................................................................................................84 5.6 Changing Setting of System Clock and CPU Clock................................................................85 5.6.1 Time required for switching between system clock and CPU clock ............................................85 5.6.2 Switching CPU clock ...

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Notes on Using 16-Bit Timer 20 ................................................................................................97 6.5.1 Restrictions when rewriting 16-bit compare register 20 .............................................................. 97 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 ...............................................................................99 7.1 Functions of 8-Bit Timer/Event Counter 00 ...

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... Flash Memory Characteristics ................................................................................................172 13.1.1 Programming environment ........................................................................................................172 13.1.2 Communication mode................................................................................................................173 13.1.3 On-board pin processing ...........................................................................................................176 13.1.4 Connection of adapter for flash writing......................................................................................179 CHAPTER 14 INSTRUCTION SET.......................................................................................................182 14.1 Operation ..................................................................................................................................182 14.1.1 Operand identifiers and writing methods...................................................................................182 14.1.2 Description of “Operation” column.............................................................................................183 14.1.3 Description of “Flag” column .....................................................................................................183 14 ...

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APPENDIX C REGISTER INDEX .........................................................................................................216 C.1 Register Name Index................................................................................................................216 C.2 Register Symbol Index.............................................................................................................218 APPENDIX D REVISION HISTORY......................................................................................................220 14 User’s Manual U11919EJ4V0UD ...

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... Format of Port Mode Register....................................................................................................................77 4-13 Format of Pull-Up Resistor Option Register...............................................................................................77 5-1 Block Diagram of Clock Generator.............................................................................................................79 5-2 Format of Processor Clock Control Register..............................................................................................80 5-3 External Circuit of System Clock Oscillator................................................................................................81 5-4 Examples of Incorrect Resonator Connection ..........................................................................................82 5-5 Switching CPU Clock .................................................................................................................................85 6-1 Block Diagram of 16-Bit Timer 20 ..............................................................................................................87 LIST OF FIGURES (1/3) Title User’s Manual U11919EJ4V0UD Page 15 ...

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Figure No. 6-2 Format of 16-Bit Timer Mode Control Register 20 .....................................................................................90 6-3 Format of Port Mode Register 5.................................................................................................................91 6-4 Settings of 16-Bit Timer Mode Control Register 20 for Timer Interrupt Operation .....................................92 6-5 Timer Interrupt Operation Timing...............................................................................................................93 6-6 Settings ...

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... Reset Timing by Overflow in Watchdog Timer.........................................................................................169 12-4 Reset Timing by RESET Input in STOP Mode.........................................................................................169 13-1 Environment for Writing Program to Flash Memory .................................................................................172 13-2 Communication Mode Selection Format ..................................................................................................173 13-3 Example of Connection with Dedicated Flash Programmer.....................................................................174 13-4 V Pin Connection Example ...................................................................................................................176 PP 13-5 Signal Conflict (Input Pin of Serial Interface) ...........................................................................................177 13-6 Abnormal Operation of Other Device ...

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... Table No. 2-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins ...............................................34 3-1 Internal ROM Capacity...............................................................................................................................41 3-2 Vector Table...............................................................................................................................................41 3-3 Internal High-Speed RAM Capacity ...........................................................................................................42 3-4 Special Function Registers ........................................................................................................................53 4-1 Port Functions............................................................................................................................................65 4-2 Port Configuration ......................................................................................................................................66 4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions.....................................76 5-1 Configuration of Clock Generator ..............................................................................................................79 5-2 Maximum Time Required for Switching CPU Clock...................................................................................85 6-1 Configuration of 16-Bit Timer 20 ...

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... Hardware Status After Reset ...................................................................................................................170 Differences Between µ PD78F9026A and Mask ROM Versions ..............................................................171 13-1 13-2 Communication Mode List........................................................................................................................173 13-3 Pin Connection List ..................................................................................................................................175 14-1 Operand Identifiers and Writing Methods ................................................................................................182 18-1 Surface Mounting Type Soldering Conditions..........................................................................................206 LIST OF TABLES (2/2) Title User’s Manual U11919EJ4V0UD ...

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Features • ROM and RAM capacity Item Part Number µ PD789022 ROM µ PD789024 µ PD789025 µ PD789026 µ PD78F9026A Flash memory • Minimum instruction execution time can be changed from high-speed (0.4 µ low-speed (1.6 µ ...

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Ordering Information Part Number µ PD789022GB-×××-8ES µ PD789024GB-×××-8ES µ PD789025GB-×××-8ES µ PD789026GB-×××-8ES µ PD78F9026AGB-8ES ××× indicates ROM code suffix. Remark CHAPTER 1 GENERAL Package 44-pin plastic LQFP (10 × 10) 44-pin plastic LQFP (10 × 10) 44-pin plastic LQFP ...

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... P43/KR3 8 P42/KR2 9 P41/KR1 10 P40/KR0 Caution Connect the IC pin directly to V The item in parentheses applies to the µ PD78F9026A only. Remark ASCK: Asynchronous serial clock CPT2: Capture trigger input IC: Internally connected INTP0 to INTP2: Interrupt from peripherals KR0 to KR7: ...

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Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 µ 30-pin PD789074 µ 28-pin PD789014 ...

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The major functional differences between the subseries are listed below. Series for general-purpose applications and LCD drive Function ROM Capacity Subseries 8-Bit 16-Bit Watch WDT (Bytes) µ PD789046 Small scale µ PD789026 ...

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Series for ASSP Function ROM Capacity Subseries 8-Bit 16-Bit Watch WDT (Bytes) µ PD789800 USB µ PD789842 Inverter Note control µ PD789850 On-chip ...

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Block Diagram 8-bit timer TI0/TO0/P50 event/counter 00 TO2/P51 16-bit timer 20 CPT2/INTP2/P32 Watchdog timer SCK0/ASCK/P20 Serial SO0/TxD/P21 interface 00 SI0/RxD/P22 INTP0/P30 to INTP2/ CPT2/P32 Interrupt control KR0/P40 to KR7/P47 Remarks 1. The internal ROM and internal high-speed RAM capacities ...

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Overview of Functions Part Number Item Internal memory ROM High-speed RAM Minimum instruction execution time Instruction set I/O ports Serial interface Timer Timer outputs Vectored interrupt Maskable sources Non-maskable Power supply voltage Operating ambient temperature Package The outline of ...

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List of Pin Functions (1) Port pins Pin Name I/O P00 to P07 I/O Port 0 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can ...

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... DD1 − V Ground potential for ports SS0 − V Ground potential (except for ports) SS1 − IC Internally connected. Connect this pin directly to the V pin. − V Flash memory programming mode setting. PP Apply high voltage during program write/verify. CHAPTER 2 PIN FUNCTIONS Function or V SS0 ...

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Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). When these ...

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P30 to P32 (Port 3) These pins constitute a 3-bit I/O port. In addition, they also function as external interrupt and capture edge inputs. This port can drive LEDs directly. Port 3 can be specified in the following operation ...

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... X1, X2 These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.9 NC The NC (non-connection) pin is not connected internally. Connect this pin to the V left open). 2.2. This is the positive power supply pin. ...

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... SS1 2.2.13 IC (mask ROM version only) The IC (internally connected) pin is used to set the µ PD789026 Subseries in the test mode for testing before shipment. In the normal operating mode, directly connect the IC pin to the V possible potential difference is generated between the IC pin and V these pins, or external noise is superimposed on the IC pin, the user program may not run correctly. • ...

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... Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type ...

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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-X Pullup enable V DD0 Output data P-ch Output N-ch disable Port read CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 8-J Pullup enable Output data Output disable V ...

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CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The PD789026 Subseries can access memory space. Figures 3-1 through 3-5 show the memory maps. FFFFH Special function registers FF00H FEFFH Internal high-speed RAM FE00H FDFFH Data memory space 1000H ...

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Figure 3-2. Memory Map ( PD789024) FFFFH Special function registers FF00H FEFFH Internal high-speed RAM FE00H FDFFH Data memory space 2000H 1FFFH Program Internal ROM memory space 8,192 0000H CHAPTER 3 CPU ARCHITECTURE 256 8 bits 256 8 bits Reserved ...

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FFFFH Special function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH Data memory space 3000H 2FFFH Program memory space 0000H 38 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( PD789025) 256 8 bits 512 8 bits Reserved Internal ROM ...

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Figure 3-4. Memory Map ( PD789026) FFFFH Special function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH Data memory space 4000H 3FFFH Program Internal ROM memory space 16,384 0000H CHAPTER 3 CPU ARCHITECTURE 256 8 bits 512 8 bits Reserved ...

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Figure 3-5. Memory Map ( PD78F9026A) FFFFH Special function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH Data memory space 4000H 3FFFH Program Internal flash memory memory space 0000H 40 CHAPTER 3 CPU ARCHITECTURE 256 8 bits 512 8 bits ...

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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789026 Subseries provides internal ROM (or flash memory) with the following capacities for each ...

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Internal data memory (internal high-speed RAM) space The PD789026 Subseries provides internal high-speed RAM with the following capacities for each product. The internal high-speed RAM cannot be used as a program area for writing and executing instructions. The internal ...

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Data memory addressing The PD789026 Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FFFFH Note 2 FFFFH ), particular addressing modes can be ...

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Figure 3-7. Data Memory Addressing ( PD789024) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 8 bits FE20H FE1FH FE00H FDFFH Reserved 2000H 1FFFH Internal ROM 8,192 8 bits 0000H 44 CHAPTER ...

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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( PD789025) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved 3000H 2FFFH Internal ROM 12,288 8 ...

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Figure 3-9. Data Memory Addressing ( PD789026) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved 4000H 3FFFH Internal ROM 16,384 8 bits 0000H 46 CHAPTER ...

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CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( PD78F9026A) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved 4000H 3FFFH Internal flash memory 16,384 ...

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Processor Registers The PD789026 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. A program counter, a program status word, and a stack ...

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CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE ...

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Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high- speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration 15 ...

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General-purpose registers The general-purpose registers consist of eight 8-bit registers ( and H). Each register can be used as an 8-bit register and two 8-bit registers in pairs can be used as a ...

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Special function registers (SFR) Unlike a general-purpose register, each special function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, with operation, ...

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Table 3-4. Special Function Registers (1/2) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF10H Transmit shift register 00 Receive buffer register 00 FF16H ...

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Table 3-4. Special Function Registers (2/2) Address Special Function Register (SFR) Name FFE0H Interrupt request flag register 0 FFE1H Interrupt request flag register 1 FFE4H Interrupt mask flag register 0 FFE5H Interrupt mask flag register 1 FFECH External interrupt mode ...

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Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction ...

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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions ...

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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. ...

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Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...

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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied is the 256-byte space FE20H to FF1FH. ...

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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...

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Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified by the register specification code and functional name in the instruction code. Register addressing is carried out when an instruction ...

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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specification code in the instruction code. This addressing ...

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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...

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Functions of Ports The µ PD789026 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Alternate functions are provided in addition to the digital I/O port function. For more information on these alternate functions, see ...

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Pin Name I/O P00 to P07 I/O Port 0 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting the pull-up resistor option ...

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... This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0). When using the P00 to P07 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO). RESET input sets port 0 to input mode. ...

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... This is an 8-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 to P17 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO). RESET input sets port 1 to input mode. ...

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... When using the P20 to P22 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the data I/O and clock I/O pins of the serial interface. ...

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WR PUO PUO2 RD WR PORT Output latch (P21 PM21 Alternate function PUO: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block ...

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WR PUO PUO2 Alternate function RD WR PORT Output latch (P22 PM22 PUO: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal 70 CHAPTER 4 PORT FUNCTIONS Figure 4-6. ...

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... When using the P30 to P32 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the external interrupt input and capture edge input. ...

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... RESET input sets port 4 to input mode. Figure 4-8 shows the block diagram of port 4. Caution When using port 4 for the key return function necessary to set key return mode register 00. For details of the settings, see 10.3 (5) Key return mode register 00 (KRM00). Figure 4-8. Block Diagram of P40 to P47 ...

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... This is a 4-bit I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). When using the P50 to P53 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the data I/O pins of the timer. ...

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WR PUO PUO5 RD WR PORT Output latch (P51 PM51 Alternate function PUO: Pull-up resistor option register PM: Port mode register RD: Port 5 read signal WR: Port 5 write signal 74 CHAPTER 4 PORT FUNCTIONS Figure 4-10. ...

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Figure 4-11. Block Diagram of P52 and P53 WR PUO PUO5 RD WR PORT Output latch (P52, P53 PM52, PM53 PUO: Pull-up resistor option register PM: Port mode register RD: Port 5 read signal WR: Port 5 write ...

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Registers Controlling Port Function The following two types of registers control the ports. • Port mode registers (PM0 to PM5) • Pull-up resistor option register (PUO) (1) Port mode registers (PM0 to PM5) These registers are used to set ...

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Figure 4-12. Format of Port Mode Register Symbol PM0 PM07 PM06 PM05 PM1 PM17 PM16 PM15 PM2 PM3 PM4 PM47 PM46 PM45 PM5 PMmn 0 Output mode (output ...

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Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be ...

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Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • System clock oscillator This circuit oscillates at frequencies of 1.0 ...

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Register Controlling Clock Generator The clock generator is controlled by the following register. • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio. PCC is set with a ...

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... System Clock Oscillator 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. ...

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... Examples of incorrect resonator connection Figure 5-4 shows examples of incorrect resonator connection. Figure 5-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring SS0 SS1 (c) Wiring near high fluctuating current SS0 SS1 82 CHAPTER 5 CLOCK GENERATOR X2 (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) ...

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... Figure 5-4. Examples of Incorrect Resonator Connection (2/2) 5.4.3 Divider circuit The divider circuit divides the output of the system clock oscillator (f CHAPTER 5 CLOCK GENERATOR (e) Signal is fetched SS0 SS1 ) to generate various clocks. X User’s Manual U11919EJ4V0UD 83 ...

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Operation of Clock Generator The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • System clock f X • CPU clock f CPU • Clock to peripheral hardware ...

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Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the ...

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Functions of 16-Bit Timer 20 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture (1) Timer interrupt An interrupt is generated when the count value and compare value match. (2) Timer ...

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Configuration of 16-Bit Timer 20 16-bit timer 20 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer 20 Item 16 bits × 1 (TM20) Timer counter Compare register: 16 bits × 1 (CR20) Registers Capture register: 16 ...

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This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when they match, generates an interrupt request (INTTM2). CR20 is set with a 16-bit memory ...

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Registers Controlling 16-Bit Timer 20 The following two registers control 16-bit timer 20 (TM20). • 16-bit timer mode control register 20 (TMC20) • Port mode register 5 (PM5) (1) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode ...

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Figure 6-2. Format of 16-Bit Timer Mode Control Register 20 7 <6> 5 Symbol TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TOD20 0 Timer output data Timer output data is 1. TOF20 0 Clear by reset and ...

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Port mode register 5 (PM5) This register sets the input/output of port 5 in 1-bit units. To use the P51/TO2 pin for timer output, set PM51 and the output latch of P51 to 0. PM5 is set with a ...

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Operation of 16-Bit Timer 20 6.4.1 Operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count ...

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Figure 6-5. Timer Interrupt Operation Timing t Count clock TM20 count value 0000H 0001H CR20 N INTTM2 TO2 TOF20 Remark N = 0000H to FFFFH CHAPTER 6 16-BIT TIMER 20 N FFFFH 0000H 0001H N N Interrupt acknowledged Overflow flag ...

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Operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count even after the timer ...

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Capture operation The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) synchronized with a capture trigger. Set as shown in Figure 6-8 to allow 16-bit timer 20 to start the capture ...

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The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed via a counter read buffer. The counter read buffer latches the TM20 count ...

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Notes on Using 16-Bit Timer 20 6.5.1 Restrictions when rewriting 16-bit compare register 20 (1) Disable interrupts (TMMK20 = 1) and the inversion control of timer output (TOC20 = 0) before rewriting the compare register (CR20). If CR20 is ...

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B> When rewriting using 16-bit access <1> Disable interrupts (TMMK20 = 1) and the inversion control of timer output (TOC20 = 0). <2> Rewrite CR20 (16 bits). <3> Wait for one cycle or more of the count clock. <4> ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.1 Functions of 8-Bit Timer/Event Counter 00 8-bit timer/event counter 00 has the following functions. • Interval timer • External event counter • Square wave output (1) 8-bit interval timer When 8-bit timer/event counter ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.2 Configuration of 8-Bit Timer/Event Counter 00 8-bit timer/event counter 00 consists of the following hardware. Table 7-3. Configuration of 8-Bit Timer/Event Counter 00 Item 8 bits × 1 (TM00) Timer counter Compare register: ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.3 Registers Controlling 8-Bit Timer/Event Counter 00 The following two registers are used to control 8-bit timer/event counter 00. • 8-bit timer mode control register 00 (TMC00) • Port mode register 5 (PM5) (1) ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 (2) Port mode register 5 (PM5) This register sets port 5 input/output in 1-bit units. When using the P50/TI0/TO0 pin for timer output, set PM50 and the output latch of P50 to 0. PM5 ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.4 Operation of 8-Bit Timer/Event Counter 00 7.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 00 (CR00) ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 Figure 7-4. Interval Timer Operation Timing t Count clock TM00 count value 00 01 CR00 N TCE00 Count start INTTM0 TO0 Interval time Interval time = ( × t Remark where N ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI0/P50/TO0 pin by using timer counter 00 (TM00). To operate 8-bit timer/event counter 00 ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.4.3 Operation as square wave output 8-bit timer/event counter 00 can generate a square wave output of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 00 (CR00) in ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 Figure 7-6. Square Wave Output Timing Count clock TM00 count value 00 01 CR00 N TCE00 Count start INTTM0 Note TO0 Note The initial value of TO0 at output enable (TOE00 = 1) becomes ...

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 00 7.5 Notes on Using 8-Bit Timer/Event Counter 00 (1) Error on starting timer An error clock occurs after the timer has been started until a match signal is generated. This ...

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Functions of Watchdog Timer The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The ...

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Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Control registers Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer ...

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Registers Controlling Watchdog Timer The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the ...

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Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. ...

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Operation of Watchdog Timer 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time ...

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Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1 respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt ...

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... It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit. The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL Series, 78K Series, and 17K Series, which have a conventional on-chip synchronous serial interface. ...

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Receive buffer register (RXB00/SIO00) Direction controller Receive shift RxD/SI0/P22 register (RXS00) TxD/SO0/P21 PM21 Receive controller PM20 ASCK/SCK0/P20 Serial operation mode register 00 (CSIM00) Note For the configuration of the baud rate generator, see Figure 9-2. Figure 9-1. Block Diagram of ...

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BRGC00 write TXE00 Transmit clock 1/2 Receive clock 1/2 Clear CSCK00 CSIE00 RXE00 CSIE00 Start bit detection BRGC00 write RXE00 Figure 9-2. Block Diagram of Baud Rate Generator Clear Clear 3-bit counter 4 3-bit counter Clear TPS003 TPS002 TPS001 TPS000 ...

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Transmit shift register 00 (TXS00) This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data. If the data length is specified as 7 bits, bits the ...

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Registers Controlling Serial Interface 00 The following four registers are used to control serial interface 00. • Serial operation mode register 00 (CSIM00) • Asynchronous serial interface mode register 00 (ASIM00) • Asynchronous serial interface status register 00 (ASIS00) ...

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Asynchronous serial interface mode register 00 (ASIM00) This register is set when using serial interface 00 in the asynchronous serial interface mode. ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. ...

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Table 9-2. Operating Mode Settings of Serial Interface 00 (1) Operation stop mode ASIM00 CSIM00 PM22 TXE00 RXE00 CSIE00 DIR00 CSCK00 × × × Note Other than above (2) 3-wire serial I/O mode ASIM00 CSIM00 PM22 ...

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Asynchronous serial interface status register 00 (ASIS00) This register indicates the type of error when a reception error occurs in the asynchronous serial interface mode. ASIS00 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ...

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Baud rate generator control register 00 (BRGC00) This register is used to set the serial clock of serial interface 00. BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Figure 9-6. Format of ...

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The baud rate transmit/receive clock to be generated is either a divided system clock signal signal divided from the clock input to the ASCK pin. (a) Generation of baud rate transmit/receive clock from system clock The transmit/receive clock ...

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CHAPTER 9 SERIAL INTERFACE 00 (b) Generation of baud rate transmit/receive clock from external clock of ASCK pin The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate generated from the clock input ...

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Operation of Serial Interface 00 Serial interface 00 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer ...

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Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol <7> <6> 5 ASIM00 TXE00 RXE00 PS001 TXE00 0 Transmit operation stopped 1 Transmit ...

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Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communications at the desired transfer rate ...

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Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol <7> <6> 5 ASIM00 TXE00 RXE00 PS001 TXE00 0 Transmit operation stopped Transmit operation ...

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Asynchronous serial interface status register 00 (ASIS00) ASIS00 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS00 to 00H. Symbol ASIS00 PE00 0 Parity error did not occur ...

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Baud rate generator control register 00 (BRGC00) BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H Symbol BRGC00 TPS003 TPS002 TPS001 TPS000 TPS003 TPS002 TPS001 ...

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Table 9-5. Example of Relationship Between System Clock and Baud Rate Baud Rate (bps) 1,200 2,400 4,800 9,600 19,200 38,400 76,800 Caution Be sure not to select during operation at f exceeds the baud rate limit. (ii) ...

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CHAPTER 9 SERIAL INTERFACE 00 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character ...

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Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and ...

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CHAPTER 9 SERIAL INTERFACE 00 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data ...

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Reception When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the ...

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Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. Upon data reception, an error flag is set in asynchronous serial interface status register 00 (ASIS00). Receive error causes ...

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... To read the receive data stored in receive buffer register 00 (RXB00), read while reception is enabled (RXE00 = 1). Remark However necessary to read receive data after reception has stopped (RXE00 = 0), read using either of the following methods. (a) Read after setting RXE00 = 0 after waiting for one cycle or more of the source clock selected by BRGC00 ...

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CHAPTER 9 SERIAL INTERFACE 00 (3) Cautions related to UART mode (a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then ...

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... I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK0), serial output (SO0), and serial input (SI0) ...

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Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. When the 3-wire serial I/O mode is selected, ASIM00 must be set to 00H. Symbol ...

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... If the internal clock is used as the serial clock for 3-wire serial I/O mode, set the TPS000 to TPS003 bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula. When the serial clock is input from external, setting BRGC00 is not necessary. Serial clock frequency = ...

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CHAPTER 9 SERIAL INTERFACE 00 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 00 (TXS00/SIO00) and receive shift register ...

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CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other ...

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Note 1 Interrupt Type Priority Name − Non-maskable INTWDT Maskable 0 INTWDT 1 INTP0 2 INTP1 3 INTP2 4 INTSR INTCSI0 5 INTST 6 INTTM0 7 INTTM2 8 INTKR Notes 1. The priority is the priority applicable when two or ...

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Figure 10-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Interrupt request (B) Internal maskable interrupt Interrupt request IF (C) External maskable interrupt INTM0, KRM00 Interrupt request Edge detector INTM0: External interrupt mode register 0 KRM00: Key return mode ...

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Registers Controlling Interrupt Function The following five registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 and IF1) • Interrupt mask flag registers (MK0 and MK1) • External interrupt mode register 0 (INTM0) • ...

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Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed cleared to 0 upon acknowledgement of an interrupt request, upon ...

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Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 ...

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External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 10-4. Format of External ...

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Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status of the interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped to the PSW. ...

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... Detected (at the falling edge of port 4) Cautions 1. Be sure to set bits When KRM00n is set to 1, the corresponding pin is connected to a pull-up resistor unless output mode. In output mode, the pull-up resistor is not connected. 3. Before setting KRM00, set bit 0 of MK1 (KRMK00 = 1) to disable interrupts. ...

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Interrupt Servicing Operation 10.4.1 Non-maskable interrupt request acknowledgement operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable ...

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Figure 10-8. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement (watchdog timer mode (non-maskable interrupt Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT: Figure 10-9. Non-Maskable Interrupt Request Acknowledgement Timing CPU processing Instruction TMIF4 ...

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Maskable interrupt request acknowledgement operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared vectored interrupt request is acknowledged in the ...

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Figure 10-11. Interrupt Request Acknowledgement Processing Algorithm No ××IF: Interrupt request flag ××MK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgement (1 = enable disable) 156 CHAPTER 10 INTERRUPT FUNCTIONS Start ×× ...

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Figure 10-12. Interrupt Request Acknowledgement Timing (Example of MOV A, r) Clock CPU MOV A, r Interrupt If an interrupt request flag (××IF) is set before instruction clock 10) under execution becomes n − 1, ...

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Main processing INTxx During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and nesting occurs. The EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgement enable state is set. Example 2. ...

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Interrupt request hold Some instructions may hold the acknowledgement of an interrupt request pending until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during ...

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CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is ...

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Standby function control register The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. ...

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Operation of Standby Function 11.2.1 HALT mode (1) HALT mode HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 11-1. HALT Mode Operating Status Item ...

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Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is enabled ...

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Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 11-3. Releasing HALT ...

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STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as ...

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Releasing STOP mode The STOP mode can be released by the following two types of sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt ...

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Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operation ...

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The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by program loop time detected by watchdog timer External and internal reset have no functional differences. In both cases, program ...

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Figure 12-2. Reset Timing by RESET Input X1 Normal operation RESET Internal reset signal Port pin Figure 12-3. Reset Timing by Overflow in Watchdog Timer X1 Normal operation Overflow in watchdog timer Internal reset signal Port pin Figure 12-4. Reset ...

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Table 12-1. Hardware Status After Reset Note 1 Program counter (PC) Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P0 to P5) (output latch) Port mode registers (PM0 to PM5) Pull-up resistor option register (PUO) ...

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The µ PD78F9026A is a version with the internal ROM of the mask ROM versions replaced with a flash memory. The differences between the µ PD78F9026A and the mask ROM versions are shown in Table 13-1. Table 13-1. Differences Between ...

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... Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µ PD78F9026A mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided ...

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Communication mode Use the communication mode shown in Table 13-2 to perform communication between the dedicated flash programmer and µ PD78F9026A. Communication Mode COMM PORT SIO Clock 3-wire serial SIO ch-0 100 Hz to I/O (3-wire, sync.) 1.25 MHz ...

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... Notes 1. Connect this pin when the system clock is supplied from the dedicated flash programmer. resonator is already connected to the X1 pin, the CLK pin does not need to be connected. 2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used, so connection to the CLK pin is not necessary. ...

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... Note V voltage must be supplied before programming is started Pin must be connected. Remark : If the signal is supplied on the target board, pin does not need to be connected. × × × × : Pin does not need to be connected. Table 13-3. Pin Connection List Pin Name 3-Wire Serial I/O ...

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... Serial Interface 3-wire serial I/O UART Pseudo 3-wire When connecting the dedicated flash programmer to a serial interface pin that is connected to another device on- board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such connections. 176 pin. In flash memory programming mode, a write voltage of 10 kΩ ...

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... If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored ...

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... If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed ...

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... Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 13-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O VDD2 (LVDD) VDD GND ...

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Figure 13-9. Wiring Example for Flash Writing Adapter with UART VDD2 (LVDD) VDD GND ...

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Figure 13-10. Wiring Example for Flash Writing Adapter with Pseudo 3-Wire (When P0 Is Used) VDD (2.7 to 5.5 V) GND µ ...

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This chapter lists the instruction set of the µ PD789026 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 14.1 Operation 14.1.1 Operand identifiers and writing methods ...

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Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register ...

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Operation List Mnemonic Operands MOV r, #byte saddr, #byte sfr, #byte Note Note saddr saddr sfr sfr !addr16 !addr16, A PSW, #byte A, PSW PSW [DE] ...

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Mnemonic Operands MOVW rp, #word AX, saddrp saddrp, AX Note AX, rp Note rp, AX Note XCHW AX, rp ADD A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] ADDC A, #byte saddr, #byte A, ...

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Mnemonic Operands SUBC A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] AND A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte #byte saddr, #byte ...

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Mnemonic Operands CMP A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] ADDW AX, #word SUBW AX, #word CMPW AX, #word INC r saddr DEC r saddr INCW rp DECW rp ROR A, 1 ROL ...

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Mnemonic Operands CALL !addr16 CALLT [addr5] RET RETI PUSH PSW rp POP PSW rp MOVW SP !addr16 $addr16 AX BC $saddr16 BNC $saddr16 BZ $saddr16 BNZ $saddr16 BT saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 ...

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Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r 1st Operand A ADD MOV ADDC XCH ...

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MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW saddrp SP Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, ...

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Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic instructions Compound instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP CHAPTER 14 INSTRUCTION SET AX !addr16 [addr5] BR CALL CALLT ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) A Parameter Supply voltage V V Input voltage V Output voltage V Output current, high I Output current, low I Operating ambient temperature T Storage temperature T Note Make sure ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS System Clock Oscillator Characteristics (T Resonator Recommended Circuit Ceramic resonator Crystal resonator External X1 X2 clock X1 X2 OPEN Notes 1. Indicates only oscillator characteristics. Refer to AC ...

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... CCR5.0MC3 FCR5.0MC5 Note A limiting resistor (Rd = 4.7 kΩ) is required when CSBLA1M00J58-B0 (1.0 MHz) manufactured by Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when using one of the other recommended resonators. Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS = –40 to +85° ° ° ° µ µ µ µ PD78F9026A) (2) Ceramic resonator (T A Manufacturer Part Number Murata Mfg. Co., CSBLA1M00J58-B0 Ltd. CSBFB1M00J58-R1 CST2.00MG CSTLS2M00G56-B0 CSTCC2M00G56-R0 CSTLS4M00G53-B0 CSTCR4M00G53-R0 CSTLS4M19G53-B0 CSTCR4M19G53-R0 CSTLS4M91G53-B0 ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85° Parameter Symbol Output current, high I Per pin OH Total for all pins Output current, low I Per pin OL Total for all pins Input voltage, high ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85° Parameter Symbol Note 1 Supply current I 5.0 MHz crystal oscillation DD1 (mask ROM operating mode version) I 5.0 MHz crystal oscillation DD2 HALT mode I STOP ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation (T = –40 to +85° Parameter Symbol Cycle time 2 (minimum instruction V = 1.8 to 5.5 V execution time) DD ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS (2) Serial interface –40 to +85° (i) 3-wire serial I/O mode (SCK0...Internal clock output) Parameter Symbol SCK0 cycle time 2.7 to 5.5 V KCY1 1.8 ...

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CHAPTER 15 ELECTRICAL SPECIFICATIONS (iv) UART mode (external clock input) Parameter Symbol ASCK cycle time 2.7 to 5.5 V KCY3 1 ASCK high-/low 2.7 to ...

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