Z8018218FSC Zilog, Inc., Z8018218FSC Datasheet
Z8018218FSC
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Z8018218FSC Summary of contents
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Zilog FEATURES Z8S180 MPU - Code Compatible with Zilog Z80 - Extended Instructions - Operating Frequency: 33 MHz/ MHz/3.3V - Two DMA Channels - On-Chip Wait State Generators - Two UART Channels - Two 16-Bit Timer Counters - ...
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Zilog GENERAL DESCRIPTION (Continued) D7-D0 Control A19-A0 Bus Transceiver Tx Data 85230 ESCC Rx Data Channel A ESCC Control /ROMCS Address Decode /RAMCS 8-Bit Parallel Port C MUX 85230 ESCC Ch Port C Z180 Signals or Port B ...
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Zilog 100 /INT0 1 /INT1/PC6 /INT2/PC7 A10 15 A11 A12 VSS A13 A14 20 A15 A16 A17 A18/TOUT VDD 25 A19 Figure ...
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Zilog GENERAL DESCRIPTION (Continued) 75 TXDB//HDDIS 76 /TRXCB/HA0 RXDB/HA1 /RTXCB/HA2 /SYNCB//HCS 80 /HALT /RFSH /IORQ /MRD//MREQ E 85 /M1 /WR /RD PHI VSS 90 XTAL EXTAL /WAIT /BUSACK /BUSREQ 95 /RESET /NMI /INT0 /INT1/PC6 /INT2/PC7 100 1 Figure 3. Z80182/Z8L182 ...
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Zilog Z180 CPU SIGNALS A19-A0. Address Bus (input/output, active High, tri-state). A19-A0 form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges Mbyte, and I/O data bus exchanges up to 64K. ...
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Zilog Z180 CPU SIGNALS (Continued) /NMI. Non-maskable interrupt (input, negative edge triggered). /NMI has a higher priority than /INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal ...
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Zilog Z180 MPU DMA SIGNALS /TEND0. Transfer End 0 (output, active Low). This output is asserted active during the last write cycle of a DMA operation used to indicate the end of the block transfer. /TEND0 is multiplexed ...
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Zilog Z85230 ESCC SIGNALS (Continued) /SYNCA, /SYNCB. Synchronization (inputs/outputs, active Low). These pins can act as either inputs, outputs part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are ...
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Zilog /W//REQB. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This pin is similar in functionality to /W//REQA but is applicable on 16550 MIMIC INTERFACE SIGNALS HD7-HD0. Host ...
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Zilog EMULATION SIGNALS EV1, EV2. Emulation Select (input). These two pins determine the emulation mode of the Z180 MPU (Table 1). Mode EV2 SYSTEM CONTROL SIGNALS ST. Status (output, active High). This ...
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Zilog MULTIPLEXED PIN DESCRIPTIONS A18/T During Reset, this pin is initialized as an A18 pin. OUT. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, The T function is selected. If TOC1 and ...
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Zilog Ports B and C Multiplexed Pin Descriptions Ports B and C are pin multiplexed with the Z180 ASCI functions and part of ESCC channel A. The MUX function is controlled by bits 7-5 in the System Configuration Register. The ...
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Zilog Table 5. Primary, Secondary and Tertiary Pin Functions Pin Number 1st VQFP QFP Function ...
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Zilog MULTIPLEXED PIN DESCRIPTIONS (Continued) Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number 1st VQFP QFP Function CKA1//TEND0 43 46 TxS 44 47 CKS 45 48 /DREQ1 ...
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Zilog Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number 1st VQFP QFP Function 71 74 RxDA 72 75 /TRxCA 73 76 TxDA 74 77 /DCDB 75 78 /CTSB 76 79 TxDB 77 80 /TRxCB 78 81 RxDB ...
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Zilog Z80182/Z8L182 FUNCTIONAL DESCRIPTION Functionally, the on-chip Z182 MPU and ESCC same as the discrete devices (Figure 1). Therefore, for a detailed description of each individual unit, refer to the Z182 MPU FUNCTIONAL DESCRIPTION This unit provides all the capabilities ...
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Zilog Z182 CPU The Z182 CPU is 100% software compatible with the Z80 CPU and has the following additional features: Faster Execution Speed. The Z182 CPU is “fine tuned,” making execution speed, on average, 10% to 20% faster than the ...
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Zilog ™ Z85230 ESCC FUNCTIONAL DESCRIPTION The Zilog Enhanced Serial Communication Controller ™ ESCC is a dual channel, multiprotocol data communication peripheral. The ESCC functions as a serial-to-parallel, parallel-to-serial converter/controller. The ESCC can be software-configured to satisfy a wide variety ...
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Zilog The following features are common to both the ESCC and the CMOS SCC: Two independent full-duplex channels Synchronous/Isochronous data rates 1/4 of the PCLK using external clock source - Mbits/sec at 20 MHz ...
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Zilog ™ Z85230 ESCC BLOCK DIAGRAM For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block diagram of the discrete ESCC, which was integrated into the Z182. The /INT line ...
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Zilog 16550 MIMIC INTERFACE FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has a 16550 MIMIC interface that allows it to mimic the 16550 device. It has all the interface pins necessary to connect to the PC/XT/AT bus. It contains the complete register set ...
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Zilog 16550 MIMIC FIFO DESCRIPTION The receiver FIFO consists of a 16-word FIFO capable of storing eight data bits and three error bits for each character stored (Figure 7). Parity error, Framing error and Break detect bits are stored along ...
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Zilog Error Description Error in At least one data byte available RCVR in FIFO with one error FIFO *TEMT Transmitter empty † *THRE Transmitter holding register is empty Break Break occurs when Detect received data input is held in logic-0 ...
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Zilog 16550 MIMIC FIFO DESCRIPTION (Continued) The PC interface may be interrupted when bytes are available in the receiver FIFO by setting bits 6 and 7 in the FCR (FIFO Control Register, PC address 02H) ...
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Zilog On the MPU interface, the transmitted data available can be programmed to interrupt the MPU bytes of available data by seeing the appropriate value in the MPU FSCR control register (MPU write only ...
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Zilog Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER The Z80182 Rev DA implements double buffering for the transmitter in 16450 mode and sets the TEMT bit in the LSR Register automatically. When this feature is enabled and character delay emulation ...
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Zilog PARALLEL PORTS FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only). PROGRAMMING The following subsections explain and define the ...
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Zilog PROGRAMMING (Continued) Table 9. Z80182/Z8L182 ESCC, PIA and MISC Registers Register Name WSG Chip Select Register Z80182 Enhancements Register PC Data Direction Register PC Data Register Interrupt Edge/Pin MUX Control ESCC Chan A Control Register ESCC Chan A Data ...
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Zilog Z182 MPU CONTROL REGISTERS Figures 10 through 50 refer to the Z80182/Z8L182 MPU Control registers. For additional information, refer to the Z8S180 Product Specification and Technical Manual. ASCI CHANNELS CONTROL REGISTERS CNTLA0 MPE Bit RE Upon RESET 0 0 ...
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Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLA1 Bit MPE RE TE Upon RESET R/W R/W R/W R/W 3- Addr 01H CKA1D MPBR/ MOD2 MOD1 MOD0 EFR ...
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Zilog CNTLB0 Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W † /CTS - Depending on the condition of /CTS pin Cleared to 0. General Divide Ratio (Divide Ratio = 10) SS ...
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Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLB1 /CTS/ Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W R/W General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 ...
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Zilog STAT0 RDRF OVRN Bit 0 Upon Reset R R/W †† /CTS0 Pin STAT1 Bit RDRF OVRN 0 Upon Reset R R/W DS971820600 Addr 04H PE FE RIE /DCD0 ...
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Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) TDR0 Write Only Addr 06H Transmit Data Figure 15. ASCI Transmit Data Register (Ch. 0) TDR1 Write Only Addr 07H ...
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Zilog CSI/O REGISTERS CNTR Bit EF EIE Upon Reset 0 R R/W R/W SS2 Baud Rate 000 Ø 001 Ø 010 Ø 011 Ø Figure 22. CSI/O Transmit/Receive Data Register DS971820600 ...
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Zilog TIMER DATA REGISTERS TMDR0L Read/Write Addr 0CH Figure 23. Timer 0 Data Register L TMDR1L Read/Write Addr 14H Figure 24. Timer 1 Data ...
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Zilog TIMER CONTROL REGISTER TCR Bit TIF1 TIF0 Upon Reset TOC1,0 A15/TOUT 00 Inhibited DS971820600 Addr 10H TIE1 TIE0 TOC1 TOC0 ...
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Zilog FREE RUNNING COUNTER CPU CONTROL REGISTER DMA REGISTERS Figure 34. DMA 0 Source Address Registers 3- FRC Read Only Addr 18H ...
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Zilog DMA REGISTERS DAR0L Read/Write Addr 23H DA7 DA0 DAR0H Read/Write Addr 24H DA15 DA8 DAR0B Read/Write Addr 25H DA19 DA16 - - - - Bits 0-2 (3) are used for DAR0B A19, A18, A17, A16 DMA Transfer Request x ...
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Zilog DMA REGISTERS (Continued) DSTAT Bit DE1 DE0 /DWE1 Upon Reset R/W R/W R/W W DMODE Bit - - DM1 Upon Reset 1 1 R/W R/W DM1, 0 Destination I/O ...
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Zilog DCNTL Bit MWI1 MWI0 Upon Reset 1 1 R/W R/W R/W * MWI1, 0 No. of Wait States DMSi 1 0 DM1 Note using ROM/RAM Chip Select wait ...
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Zilog MMU REGISTERS CBR Bit CB7 CB6 Upon Reset 0 0 R/W R/W R/W BBR Bit BB6 BB7 Upon Reset 0 0 R/W R/W R/W CBAR Bit CA3 CA2 Upon Reset 1 1 R/W R/W R/W Figure 45. MMU Common/Bank ...
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Zilog SYSTEM CONTROL REGISTERS IL Bit IL7 IL6 Upon Reset 0 0 R/W R/W R/W ITC Bit TRAP UFO Upon Reset 0 0 R/W R/W R RCR Bit REFE REFW Upon Reset 1 1 R/W R/W R/W CYC1, 0 Interval ...
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Zilog SYSTEM CONTROL REGISTERS (Continued) OMCR M1E /M1TE /IOC Bit Upon Reset R/W W R/W R/W Note: This register should be programmed to 0x0xxxxxb (x = don't care part of Initialization. Figure 49. Operation Mode ...
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Zilog ADDITIONAL FEATURES ON THE Z182 MPU The following is a detailed description of the enhancements to the Z8S180 from the standard Z80180 in the areas of STANDBY, IDLE, and STANDBY-QUICK RECOVERY modes. Add-On Features There are five different power-down ...
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Zilog STANDBY Mode Exit with BUS REQUEST Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the /BUSREQ input is asserted; the crystal oscillator is then restarted. An internal ...
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Zilog When the part is in IDLE mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the CLKOUT, is stopped completely. IDLE mode is exited in a similar way as STANDBY ...
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Zilog CPU Control Register Bit 7. Clock Divide Select. Bit 7 of the CCR allows the programmer to set the internal clock to divide the external clock the bit is 0 and divide-by-one if the bit is ...
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Zilog ™ Z85230 ESCC CONTROL REGISTERS See Figures 52 and 53 for the ESCC Control registers. For additional information, refer to the ESCC Product Specification /Technical Manual. The Z80182/Z8L182 has two ESCC channels. They can be accessed in any page ...
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Zilog PROGRAMMING THE ESCC The ESCC contains write registers in each channel that are programmed by the system separately to configure the functional uniqueness of the channels. In the ESCC, the data registers are directly addressed by selecting a High ...
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Zilog CONTROL REGISTERS Write Register 0 (non-multiplexed bus mode Register Register Register Register ...
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Zilog CONTROL REGISTERS (Continued) Sync7 Sync6 Sync1 Sync0 Sync7 Sync6 Sync3 Sync2 ADR7 ADR6 ADR7 ADR6 Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 0 1 Figure 52. Write Register Bit Functions (Continued) 3- ...
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Zilog WR 7' Prime Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Rx FIFO Int Level DTR/REQ Timing Mode Tx FIFO Int Level Extended Read Enable 32-bit CRC Enable Write Register ...
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Zilog CONTROL REGISTERS (Continued) Write Register TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Write Register TC8 TC9 TC10 TC11 TC12 TC13 ...
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Zilog Read Register Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort Read Register All Sent Residue ...
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Zilog CONTROL REGISTERS (Continued) Read Register Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing Read Register ...
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Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Figures 54 through 65 describe miscellaneous registers that control the Z182 configuration, RAM/ROM chip select, interrupt and various status and timers ...
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Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Table 12b. Data Bus Direction (Z182 Bus Master) Interrupt Acknowledge Transaction Intack For On-Chip Peripheral (IEI=1) Z80182/Z8L182 Data Bus (DD =0) OUT Z80182/Z8L182 Data Bus Out (DD =1) OUT Table 13a. Data Bus ...
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Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Bit 3 Disable ROMs If this bit disables the ROMCS pin addresses below the ROM boundary set by the ROMBR register will cause the ROMCS pin ...
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Zilog /RAMCS AND /ROMCS REGISTERS (Continued) RAMUBR, RAMLBR RAM Upper Boundary Range, RAM Lower Boundary Range These two registers specify the address range for the /RAMCS signal. When accessed memory addresses are less than or equal to the value programmed ...
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Zilog INTERRUPT EDGE/PIN MUX REGISTER Bits 7-6. These bits control the interrupt capture logic for the external /INT2 PIN. When programmed as ‘0X’, the /INT2 pin performs as the normal level ...
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Zilog INTERRUPT EDGE/PIN MUX REGISTER (Continued) Bit 0. Programming this bit to 1 selects a 16 cycle wait delay on recovery from HALT. Halt Recovery is disabled if bit 5 of the enhancement register is set ...
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Zilog 16550 MIMIC INTERFACE REGISTERS MIMIC Master Control Register (MMC) The 16550 MIMIC interface is controlled by the MMC register. Setting it allows for different modes of operation such as using the 8-bit counters, DMA accesses, and which IRQ structure ...
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Zilog IUS/IP Register The IUS/IP Register is used by the Z180 the source of the interrupt. This register will have the appropriate bit set when an interrupt occurs ...
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Zilog Interrupt Enable Register The IE Register allows each of the 16550/8250 interrupts ™ to the Z180 MPU to be masked off individually or globally ...
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Zilog Interrupt Vector Register (Continued) Table 16. Interrupt Status Bits Bits Interrupt Request 000 NO IRQ 001 FCR or Tx OVRN IRQ 010 DLL/DLM IRQ 011 LCR IRQ* 100 MCR IRQ* 101 RBR IRQ 110 TTO IRQ ...
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Zilog Bit 0 16450 MIMIC Mode Enable (Reset value=0) This bit = 1 will force the mimic into 16450 mode. Bit 0 in the FCR reg is forced to zero as well as the mimic internal FIFO enable. When used, ...
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Zilog Transmit And Receive Timers (Continued) When a write from the PC/XT/AT is made to the Transmit Holding Register, an interrupt to the Z180 MPU is generated. The Z180 MPU then reads the data in the Transmit Holding Register. Upon ...
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Zilog 16550 MIMIC REGISTERS The Z80182/Z8L182 contains the following set of registers for interfacing with the PC/XT/AT. – Receive Buffer Register – Transmit Holding Register – Interrupt Enable Register – Interrupt Identification Register – FIFO Control Register – Line Control ...
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Zilog 16550 MIMIC REGISTERS (Continued) FIFO Control Register Bit 6 and Bit 7 RCVR trigger LSB and MSB bits This 2-bit field determines the number of available bytes in the receiver FIFO before an interrupt to the PC occurs (see ...
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Zilog Although this bit is disabled by default advised that this bit is enabled to prevent interrupt conflict between MIMIC and ESCC interrupts ...
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Zilog 16550 MIMIC REGISTERS (Continued) Line Status Register Bit 7 Error in RCVR FIFO In 16450 mode, this bit will read logic 0. In 16550 mode this bit is set if at least one data byte is available in the ...
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Zilog Figure 76. Line Control Register (PC Read/Write, Address 03H) (Z180 MPU Read Only, Address xxF3H) Line Control Register Bit 7 Divisor Latch Access ...
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Zilog 16550 MIMIC REGISTERS (Continued) Modem Status Register Bit 7 Data Carrier Detect This bit must be written by the Z180 MPU. Bit 6 Ring Indicator This bit must be written by the Z180 MPU. Bit 5 Data Set Ready ...
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Zilog Z80182 ENHANCEMENTS REGISTER Bit <7-6> Reserved Bit 5 Force Z180 Halt Mode If this bit is set disables the 16 cycle halt recovery and halt control over the busses and pins. This bit is used to ...
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Zilog PARALLEL PORTS REGISTERS The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output. The Ports consist of two registers the Port Direction Control Register and the Port Data Register. The Port and direction ...
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Zilog The data direction register determines which are inputs and outputs in the PC Data Register. When a bit is set to 1 the corresponding bit in the PC Data Register is an input. If the bit is 0, then ...
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Zilog Z80182/Z8L182 MIMIC DMA CONSIDERATIONS For the PC Interface, the 16550 device has two modes of operation that need to be supported by the MIMIC. In single transfer mode, the DMA request line for the receiver goes active whenever there ...
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Zilog EMULATION MODES (Continued) Table 21. Emulation Mode 1 Normal Signal Mode 0 PHI Output /M1 Output /MREQ,/MRD Output /IORQ Output /RD Output /WR Output /RFSH Output /HALT Output ST Output E Output /BUSACK Output /WAIT Input A19,A18/T Output OUT ...
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Zilog ABSOLUTE MAXIMUM RATINGS Voltage on V with respect to V ........... –0.3V to +7. Voltages on all inputs with respect to V ........................... –0. Operating Ambient Temperature ................... 0 to +70 C Storage Temperature ...
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Zilog DC CHARACTERISTICS Z80182/Z8L182 ( 10 0V, over specified temperature range unless otherwise notes Symbol Parameter V Input H Voltage IH1 /RESET, EXTAL, NMI V Input H Voltage IH2 Except /RESET, EXTAL, NMI V ...
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Zilog DC CHARACTERISTICS Z80182/Z8L182 (V = 3.3V 10 0V, over specified temperature range unless otherwise notes Symbol Parameter V Input H Voltage IH1 /RESET, EXTAL, NMI V Input H Voltage IH2 Except /RESET, EXTAL, NMI V ...
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Zilog TIMING DIAGRAMS Z180 MPU Timing Opcode Fetch Cycle ø Address 19 /WAIT 7 /MREQ 8 /IORQ /RD 9 /WR / Data IN Data OUT 63 62 /RESET 68 67 (Opcode ...
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Zilog TIMING DIAGRAMS (Continued) Ø /INTI 33 /NMI /INTSCC [4] /M1 [1] /IORQ [1] /Data IN [1] /MREQ [2] /RFSH [ /BUSREQ /BUSACK Address Data /MREQ, /RD, /WR, /IORQ /HALT Notes: [1] During /INT0 acknowledge cycle ...
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Zilog I/O Read Cycle Address 28 /IROQ 9 /RD /WR Ø /DREQi (At level sense) /DREQi (At edge sence) /TENDi ST DMA Control Signals 1] tDRQS and tDRQH are specified for the rising edge of clock ...
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Zilog TIMING DIAGRAMS (Continued) T1 Ø D7-D0 Ø BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode 3- Figure 94. E Clock Timing ...
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Zilog T2 Ø E (Example: I/O Read - Opcode Fetch) E (I/O Write) Ø A18/TOUT DS971820600 Figure 96. E ...
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Zilog TIMING DIAGRAMS (Continued) SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT 3- Figure 98. SLEEP Execution Cycle ...
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Zilog CSI/O Clock Transmit Data (Internal Clock) Transmit Data (External Clock) Receive Data (Internal Clock) Receive Data (External Clock) /MREQ /RAMCS /ROMCS /IORQ /IOCS DS971820600 tcyc ...
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Zilog TIMING DIAGRAMS (Continued Address /MREQ /RD /WR /MRD 9 7 /MWR 22 65 EXTAL VIH1 VIH1 VIL1 Figure 102. External Clock Rise Time and Fall Time 3- ...
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Zilog Z8S180 AC CHARACTERISTICS No. Sym Parameter 1 tcyc Clock Cycle Time 2 tCHW Clock Pulse Width (High) 3 tCLW Clock Pulse Width (Low) 4 tcf Clock Fall Time 5 tcr Clock Rise Time 6 tAD Address Valid from Clock ...
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Zilog Z8S180 AC CHARACTERISTICS (Continued) No. Sym Parameter 41 tRFD1 Clock Rise to /RFSH Fall Delay 42 tRFD2 Clock Rise to /RFSH Rise Delay 43 tHAD1 Clock Rise to /HALT Fall Delay 44 tHAD2 Clock Rise to /HALT Rise Delay ...
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Zilog ESCC Timing Ø /WR /RD /W//REQ Wait /W//REQ Request /DTR//REQ Request /INT No. Symbol Parameter 1 TdWR(W) /WR Fall to Wait Valid Delay 2 TdRD(W) /RD Fall to Wait Valid Delay 3 TdWRf(REQ) /WR Fall to /W//REQ Not Valid ...
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Zilog AC CHARACTERISTICS (Continued) Z85230 General Timing Diagram PCLK /W//REQ Request /W//REQ Wait /RTxC, /TRxC Receive 4 RxD 8 /SYNC External /TRxC, /RTxC Transmit TxD 13 /TRxC Output /RTxC /TRxC /CTS, /DCD /SYNC Input 3- ...
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Zilog No. Symbol 1 TdPC(REQ) 2 TdPC(W) 3 TsRxC(PC) 4 TsRxD(RxCr) 5 ThRxD(RxCr) 6 TsRxD(RxCf) 7 ThRxD(RxCf) 8 TsSY(RxC) 9 ThSY(RXC) 10 TsTxC(PC) 11 TdTxCf(TXD) 12 TdTxCr(TXD) 13 TdTxD(TRX) 14 TwRTxh 15 TwRTxI 16a TcRTx 16b TxRx(DPLL) 17 TcRTxx 18 ...
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Zilog AC CHARACTERISTICS (Continued) Z85230 System Timing Diagram /RTxC, /TRxC Receive /W/REQ Request /W/REQ Wait /SYNC Output /INT /RTxC, /TRxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input /INT 3- ...
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Zilog No. Symbol 1 TdRxC(REQ) 2 TdRxC(W) 3 TdRxC(SY) 4 TdRxC(INT) 5 TdTxC(REQ) 6 TdTxC(W) 7 TdTxC(DRQ) 8 TdTxC(INT) 9 TdSY(INT) 10 TdExT(INT) Notes: These AC parameters values are preliminary and subject to change without notice. [1] Open-drain output, measured ...
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Zilog General-Purpose I/O Port Timing This figure shows the timing for the Ports A, B and C. Parameters referred to in this figure appear in Tables D and E. I/O Port Timing (Output Port Data Dir. ...
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Zilog Read Write External Bus Master Timing Address A7-A0 /IORQ /RD Data /WR Data Figure 108. Read/Write External Bus Master Timing DS971820600 Data In ...
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Zilog ESCC External Bus Master Timing Valid ESCC Addr * IORQ /RD or /WR DTR/REQ Request Figure 109. ESCC External Bus Master Timing Table G. External Bus Master Interface Timing (SCC Related Timing) No. Symbol Parameter 1 TrC Valid Access ...
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Zilog 16550 MIMIC TIMING Refer to Figures 106 thru 112 for MIMIC AC Timing. HA2, HA1, HA0 /HCS /HRD /HWR No Symbol Parameter 1 tAR /HRD Delay from Address 2 tCSR /HRD Delay from /HCS 3 tAW /HWR Delay from ...
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Zilog 16550 MIMIC TIMING (Continued) HD7-HD0 /HWR Figure 111. Data Setup and Hold, Output Delay, Write Cycle HD7-HD0 /HRD Figure 112. Data Setup and Hold, Output Delay, Read Cycle Table I. Data Setup and Hold, Output Delay, Read Cycle No. ...
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Zilog No. Sym Parameter 13 tRDD /HRD to Driver Enable/Disable Note: These AC parameter values are preliminary and are subject to change without notice. /WR (MPU) RBR HINTR (Trigger Level) HINTR (Line Status RDR /HRD LSR /HRD RBR DS971820600 P ...
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Zilog 16550 MIMIC TIMING (Continued) No. Sym Parameter 14 tSINT Delay from Stop to Set Interrupt 15 tRINT Delay from /HRD (RD RBR or RD LSR) to Reset Interrupt Note: These AC parameter values are preliminary and are subject to ...
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Zilog No. Sym Parameter 16 tHR Delay from /WR (WR THR) to Reset Interrupt 17 TSTI Delay from Stop to Interrupt (THRE) 18 TIR Delay from /RD (RD IIR) to Reset Interrupt (THRIE) /HRD RD_RBR /WR (MPU) RCVR FIFO (First ...
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Zilog 16550 MIMIC TIMING (Continued) Table M. RCVR FIFO Bytes Other Than First No Sym Parameter 19 tRXi Delay from /HRD RBR to /HRxRDY Inactive 20 TWxi Delay from Write to /HTxRDY Inactive 21 tSXa Delay From Start to /HTxRDY ...
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Zilog PACKAGE INFORMATION DS971820600 100-Pin VQFP Package Diagram PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 3-107 ...
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Zilog PACKAGE INFORMATION (Continued) 3-108 100-Pin QFP Package Diagram PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
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... Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc ...