AL126 Broadcom Corporation, AL126 Datasheet
AL126
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AL126 Summary of contents
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... Flexible prioritized queueing for multimedia and data traffic Product Description The AL126 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost and scalable solution for ports is achieved through the use of low-cost buffer memory and Allayer’s TM proprietary RoX-II architecture. In addition, the AL126 supports port-based and 802.1q VLAN, 802 ...
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This document contains proprietary information which shall not be reproduced, transferred to other documents, or used for any other purpose without the prior written consent of Allayer Communications. Disclaimer Allayer Communications reserves the right to make changes, without notice, in ...
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... AL126 Overview ..................................................................................................... 5 2. Pin Descriptions....................................................................................................... 9 3. Functional Description........................................................................................... 26 3.1 RoX-II Interface............................................................................................. 26 3.2 Data Reception............................................................................................... 26 3.2.1 Illegal Frame Length .............................................................................. 26 3.2.2 Long Frames .......................................................................................... 26 3.2.3 False Carrier Events ............................................................................... 26 3.2.4 Frame Filtering....................................................................................... 27 3.3 Frame Forwarding.......................................................................................... 27 3.3.1 Broadcast Storm Control........................................................................ 28 3.3.2 Frame Transmission ............................................................................... 28 3.3.3 Preamble Regeneration .......................................................................... 28 3.4 Half Duplex Mode Operation ........................................................................ 29 3.5 Secure Mode Operation ................................................................................. 30 3.6 Address Learning ........................................................................................... 30 3.6.1 Address Aging........................................................................................ 31 3 ...
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... Reprogramming the EEPROM Configuration ....................................... 47 3.20.6 EEPROM Map ....................................................................................... 49 3.21 Register Descriptions ..................................................................................... 53 4. Timing Requirements............................................................................................. 84 5. Electrical Specifications ........................................................................................ 90 6. AL126 Mechanical Data........................................................................................ 91 7. Appendix I (VLAN Mapping Work Sheet) ........................................................... 92 8. Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 93 9. Appendix III (Suggested Memory Components)................................................... 94 10. Appendix IV (Memory Timing Requirements) ..................................................... 95 10/00 ...
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... AL126 Overview The AL126 is an eight-port 10/100 Ethernet switch chip with RoX-II expansion interface. The TM RoX-II interface is a 3.2 Gbit/s data ring (6.4 Gbit/s full-duplex) and control ring interfaces. The RoX-II bus can support up to four switch chips and one management device (AL300A router (AL3000) chip ...
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... The device also provides 64 IP multicast group addresses for IP multicast applications. The AL126 can perform IGMP frame trapping and forward them to the CPU. This allows the CPU to participate in the IGMP protocol and determine which ports should participate in the multicast session ...
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... Pin Diagram Figure 3 AL126 Pin Diagram (Top View) 10/00 Reference Only / Allayer Communications 7 ...
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... ETD3 ETA15 PBD2 PBD5 PBD17 PBD20 PBD8 PBD12 PBD15 PBD26 VSS VDD25 VSS VSS VSS VSS VDD33 VSS VSS AL126 Top View VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* ...
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... Pin Descriptions The AL126 supports MII/RMII interface. Ports 1 through 7 are globally programmed to be MII or RMII, and Port 0 is independently programmable as MII or RMII. When RMII interface is used; TXD3 and TXD2 should be left unconnected; RXD3, RXD2, TXCLK, RXDV, RXER, and COL can be left unconnected because they have internal pull ups. RXCLK0 and RXCLK3 should be connected to the 50 MHz reference clock ...
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PIN NAME PIN NO. M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0 M1RXDV M1RXCLK M1RXER M1CRS M1COL 10/00 Table 2: RMII/MII Interface (Port 1) I Transmit Data - NRZ data to be transmitted to R4 transceiver. ...
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PIN NAME PIN NO. M2TXD3 AB1 M2TXD2 AC4 M2TXD1 AC2 M2TXD0 AC1 M2TXEN AD3 M2TXCLK AD1 M2RXD3 AF2 M2RXD2 AF3 M2RXD1 AD4 M2RXD0 AE4 M2RXDV AF1 M2RXCLK AE1 M2RXER AE2 M2CRS AB2 M2COL AB4 10/00 Table 3: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M3TXD3 AF11 M3TXD2 AC12 M3TXD1 AD12 M3TXD0 AE12 M3TXEN AF12 M3TXCLK AC13 M3RXD3 AC14 M3RXD2 AD14 M3RXD1 AE14 M3RXD0 AF14 M3RXDV AF13 M3RXCLK AE13 M3RXER AD13 M3CRS AE11 M3COL AC11 10/00 Table 4: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M4TXD3 AF15 M4TXD2 AC16 M4TXD1 AD16 M4TXD0 AE16 M4TXEN AF16 M4TXCLK AC17 M4RXD3 AC18 M4RXD2 AD18 M4RXD1 AE18 M4RXD0 AF18 M4RXDV AF17 M4RXCLK AE17 M4RXER AD17 M4CRS AE15 M4COL AC15 10/00 Table 5: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M5TXD3 AC25 M5TXD2 AC26 M5TXD1 AB24 M5TXD0 AB25 M5TXEN AB26 M5TXCLK AA23 M5RXD3 Y23 M5RXD2 Y24 M5RXD1 Y25 M5RXD0 Y26 M5RXDV AA26 M5RXCLK AA25 M5RXER AA24 M5CRS AC24 M5COL AD25 10/00 Table 6: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M6TXD3 R26 M6TXD2 P23 M6TXD1 P24 M6TXD0 P25 M6TXEN P26 M6TXCLK N23 M6RXD3 M23 M6RXD2 M24 M6RXD1 M25 M6RXD0 M26 M6RXDV N26 M6RXCLK N25 M6RXER N24 M6CRS R25 M6COL R23 10/00 Table 7: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M7TXD3 C25 M7TXD2 C26 M7TXD1 B26 M7TXD0 A26 M7TXEN A25 M7TXCLK A24 M7RXD3 D22 M7RXD2 B22 M7RXD1 A22 M7RXD0 D21 M7RXDV A23 M7RXCLK B23 M7RXER C23 M7CRS C24 M7COL D25 10/00 Table 8: RMII/MII Interface (Port ...
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PIN NAME PIN NO. RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 AA4 RID6 AA3 RID5 AA2 RID4 AA1 RID3 AF4 RID2 AC5 ...
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... AE8 RI2CTL4 AF8 RI2CTL3 AC9 RI2CTL2 AD9 RI2CTL1 AE9 RI2CTL0 AF9 RI3CTL1 AC8 RI3CTL0 AD8 10/00 Reference Only / Allayer Communications I/O DESCRIPTION I Ring In Clock. RID [ ] and RICTL [ ] clocked in on the rising edge of RICLK. I Second Ring Control Input. I Reserved for Future Use. AL126 Revision 1.0 18 ...
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PIN NAME PIN NO. ROD31 H23 ROD30 J26 ROD29 J25 ROD28 J24 ROD27 J23 ROD26 K26 ROD25 K25 ROD24 K24 ROD23 K23 ROD22 L26 ROD21 L25 ROD20 L24 ROD19 L23 ROD18 T26 ROD17 T25 ROD16 T24 ROD15 T23 ROD14 U26 ...
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... RO3CTL1 AF21 RO3CTL0 AE21 10/00 Reference Only / Allayer Communications O Ring Out Clock. ROD [ ] and ROCTL [ ] are clocked out on the rising edge of SYSCLK. ROCLK is a delayed version of SYSCLK to drive RICLK of the next device. O Second Ring Control Output. O Reserved for Future Use. AL126 Revision 1.0 20 ...
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PIN NAME PIN NO. PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 PBA8_9 PBANC_8 10/00 ...
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PIN NAME PIN NO. PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLK Table 12: External Address Table SSRAM Interface PIN NAME ETD15 ETD14 ETD13 ETD12 ETD11 ETD10 ETD9 ETD8 ETD7 ETD6 ETD5 ETD4 ETD3 ETD2 ...
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Table 12: External Address Table SSRAM Interface (Continued) PIN NAME ETA15 ETA14 ETA13 ETA12 ETA11 ETA10 ETA9 ETA8 ETA7 ETA6 ETA5 ETA4 ETA3 ETA2 ETA1 ETA0 ETADSC# ETADV# ETGW# ETOE# ETCLK PIN NAME PIN NUMBER EEDIO EECLK 10/00 PIN NO. ...
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... I/O PHY Management Data Input and Output. Table 15: Miscellaneous Pins I/O AE10 I Device ID Number. Should be connected to AF10 EEPROM A1 and A0. The AL126 will use <0, ID1, ID0> as EEPROM address and respond to <1, ID1, ID0> in reverse EEDIO. AC19 I Reset AD19 I Test Mode Pin. This pin should be grounded for normal operation ...
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PIN NAME VDD1 B17, C22, E8, E10, M22, U5, AB14, AB18, AE3 VDD2 A3, A12, A14, B5, B24, E6, E15, E19, E21, E22, F5, G5, H5, H22, L22, M5, N22, T5, V5, W22, Y22, AA5, AA22, VSS A2, A6, A18, ...
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... Long Frames The AL126 can handle frames up to 1548 bytes. All frames longer than 1548 bytes will be discarded. If the port continues to receive data after the 1548 If the port is in half-duplex mode, the port will no longer be able to transmit or receive data during the long frame reception ...
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... If the destination port is within the same VLAN of the receiving port, the frame will be forwarded. If the frame is tagged with the IEEE 802.3ac and IEEE 802.1q VLAN tag, and the AL126 is programmed to support tagged VLAN, then tagged VLAN membership is looked up from the VLAN table. ...
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... VLAN as the receiving port. If the Flood Control Option is enabled, the AL126 will forward the frame only to the uplink port specified at the receiving port. Note: The AL126 defines a port as either a single port or a trunk, consistent with the IEEE 802.3ad Port Aggregation Standard. ...
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... The AL126 provides two non-standard options for collision handling. SuperMAC mode in Register I, System Configuration Register II, Bit 3 provides a more aggressive back-off where the back-off limit is three rather than ten. This will create a more aggressive channel capture behavior than the standard IEEE back-off algorithm ...
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... MAC address support is reduced to 0.5K, and the external table is reduced to 12K). The AL126 address table contains both the static addresses input by the CPU or the EEPROM and dynamically learned addresses. It learns the individual MAC addresses from three different sources. ...
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... If the security option is selected for the port, the AL126 will consider this a security violation. • If port is a non-protected port, the AL126 will delete the SA from the previous port’s address table and update it to the current port’ ...
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... VLAN mode is enabled by the QEnable Bit (Register 3, System Configuration IV). 3.7.1 Port Based VLAN Each port of the AL126 can be assigned to one or multiple VLANs. Frames from the source port will only be forwarded to destination ports within the same VLAN domain. A broadcast/multicast frame will be forwarded to all ports within the VLAN(s) of the source port except the source port itself ...
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... VID 0 is reserved for priority-only tagged frames, and is treated as if the frame is untagged for VLAN membership rules (the priority field is still used for selecting the proper priority queue). VID value of 0FFF is reserved by the IEEE 802.1 for future use, although the AL126 does not treat VID=0FFF in any special way. ...
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... Priority Queues and User Priority Support The IEEE 802.1p user priority value in the tag is used to queue a frame to a particular priority queue. The AL126 supports a total of four priority queues and a complete set of controls to manage these queues. User priority value the tag is arbitrarily mapped to any of the four prioritized queues by programming register 7, the Priority Queue Assignment Register ...
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... Since the AL126 performs a multicast DA search based on the full 48-bit address, it can also support private multicast groups other than standard IPMC. Both the MAC table entry and the multicast group bitmap entry needs to be set in the AL126 to initialize a multicast group. The MAC entry is formatted as <IPMC address: 01-00-5e-xx-xx- xx> ...
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... When a frame is received from any one of the trunk ports forwarded to the destination port within the VLAN. In essence, the AL126 treats a trunk as any single port within the same VLAN. If the traffic of the ports is evenly distributed among all the trunk ports, load balancing is achieved and the aggregate bandwidth of the trunk can be as high as 800 Mbit/s (full-duplex) ...
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Select the trunk ports using Port Configuration Registers (0D to 1C) Bit 9. 2. Assign the ports to the Trunk Port Register (2F to 36). The port should be assigned to the appropriate trunk using this register. For the ...
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... Register I, Bit 3. 3.11.2.1 L2 Trunk Configuration Trunk (Port Aggregation) configuration is accomplished through programming the configuration registers. The AL126 provides the capability to trap IEEE 802.3ad frames and allows the CPU to configure the aggregated links based on IEEE recommended protocol exchange. 3.11.2.2 L2 Trunk Port Assignment Each device supports up to two trunks, and each trunk can have two through eight ports as its members ...
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... Link Fail Over The AL126 supports link fail-over when one or more of the member ports is in trunk fail. This feature can be enabled by L2FailEn in Register 3, System Configuration Register IV, Bit member port in a trunk experiences a link failure, the AL126 detects this condition and divides the frame-flow that used to be assigned to the failed port to other member ports ...
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... The IPG of the jamming signal can be programmed to be either 64BT or 96BT. Collision based backpressure is generated by the AL126 only when the switch port receives a frame and its frame buffer is full. The AL126 will cease to jam the line when the line is idle. The carrier based backpressure has several advantages over collision based backpressure. ...
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... The AL126 is capable of identifying special frames and forwards them to the CPU if required. The AL126 inspects the pay load of the incoming frames, and one of the frame types selected (register 03), it will then forward the frame to the CPU. The following types of frame trapping are supported by the AL126 in addition to BPDU frames ...
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... Although this is a good way to prevent frame loss, it may not be desirable for some applications. The AL126 therefore allows users to program any queue to be able to drop frames when the number of the frames reaches the watermark programmed in that queue. ...
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... After the completion of the write transaction, the line will be put in a high impedance state. For a read operation, the AL126 will output a “10” to indicate read operation after the start of frame indicator. Following the “10” read signal will be the 5-bit ID address of the PHY device and the 5- bit register address ...
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... If a CPU is used to reprogram the PHY via the AL126, the operating mode is changed without reset or powered down. In order to ensure the link is operating in the desired mode, the PHY should renegotiate either through a command or by unplugging the RJ45. 3.18.2 PHY Management Slave Mode In the slave mode, the PHY controls the programming of the operating mode. The AL126 will continuously poll the status of the PHY devices through the serial management interface, without CPU intervention to determine the operation mode of the link ...
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... The AL126 uses the 24C02 serial EEPROM device (2048 bits organized as 256 bits x 8). The organization of EEPROM data is shown in During start up, the AL126 will try to detect the presence of the EEPROM EEPROM is present, the AL126 will be initialized by the CPU attached to the management device on the RoX-II ring initialization command is received, the device will not operate. If the reset pin is held low, the AL126’ ...
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... These four bits are 1010. The EEPROM device address should be set to the device ID number. The EECLK is an output from the AL126. EEDIO is an input if the AL126 is reading the EEPROM or an output writing to it. (See Figures 8 and 9). When accessing the EEPROM, the reset pin has to be held low before the writing operation can begin ...
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... Write Cycle Timing The EECLK is an output from the AL126 while EEDIO is a bi-directional signal. When accessing the EEPROM, the reset pin has to be held low or initialization of the AL126 must be finished before a write operation can begin. A typical write operation is shown in Start ...
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... AL126 as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well as write to the AL126, status of the register can be read from the AL126. This will serve as a very useful tool for diagnostic of an unmanaged switch. ...
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... Note: The specific bits in the register are referenced by a “X and Y” notation, where X is the register number and Y is the bit number. Table 18 shows the EEPROM addresses map cross-referenced to the register/bit set of the AL126. • Addresses 00 through 73 are for configuring the device. They are downloaded by the AL126 during reset or power up. • ...
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... Table 19: AL126 EEPROM Mapping System Configuration I System Configuration II System Configuration III System Configuration IV System Performance Tuning Vendor Specific PHY Port Monitoring Configuration Priority Queue Assignment Output Queue Management I Output Queue Management II Priority Queue Weight Round Robin RoX-II Control I RoX-II Control II Port 0 Configuration I ...
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... Table 19: AL126 EEPROM Mapping (Continued) 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 6E-6F 70-71 72-73 74-75 76-7D 10/00 Port 0 VLAN Map I Port 0 VLAN Map II Port 1 VLAN Map I Port 1 VLAN Map II Port 2 VLAN Map I Port 2 VLAN Map II Port 3 VLAN Map I Port 3 VLAN Map II Port 4 VLAN Map I Port 4 VLAN Map II Port 5 VLAN Map I Port 5 VLAN Map II ...
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... Table 19: AL126 EEPROM Mapping (Continued) 7E-85 86-8D 8E-95 96-9D 9E-A5 A6-AD AE-B5 B6-BD BE-C5 C6-CD CE-D5 D6-DD DE-E5 E6-ED EE-F5 F6-FD FE-FF 10/00 Static Entry 1 Static Entry 2 Static Entry 3 Static Entry 4 Static Entry 5 Static Entry 6 Static Entry 7 Static Entry 8 Static Entry 9 Static Entry 10 Static Entry 11 Static Entry 12 Static Entry 13 Static Entry 14 Static Entry 15 Static Entry 16 Reserved Reference Only / Allayer Communications ...
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Register Descriptions REGISTER ID 00 System Configuration I 01 System Configuration II 02 System Configuration III 03 System Configuration IV 04 System Performance Tuning 05 Vendor Specific PHY Status 06 Port Monitoring Configuration 07 Priority Queue Assignment 08 Output ...
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Port 7 Configuration I 1C Port 7 Configuration II 1D Port 0 VLAN Map I 1E Port 0 VLAN Map II 1F Port 1 VLAN Map I 20 Port 1 VLAN Map II 21 Port 2 VLAN Map I ...
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Port 7 to Trunk Port Assignment 37 Testing Control I 38 Testing Control II 39 System Status Register 3A Port 0 Operation Status 3B Port 1 Operation Status 3C Port 2 Operation Status 3D Port 3 Operation Status 3E ...
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Port 6 Default Priority/VLAN 55 Port 7 Default Priority/VLAN 56 Port 8 Default Priority/VLAN 57 Port 9 Default Priority/VLAN 58 Port 10 Default Priority/VLAN 59 Port 11 Default Priority/VLAN 5A Port 12 Default Priority/VLAN 5B Port 13 Default Priority/VLAN ...
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... STPEN 10/00 CPU Present. This bit is used to indicate if the AL126 is initialized from the EEPROM. This bit is set by the AL126 when it detects the EEPROM is not present and its configuration is not initialized. The device assumes that a CPU is present and waits for the CPU to initialize this device. ...
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... Port Outgoing Frame Flow Monitoring (port snooping) Enable Control. The monitored and snooping port configuration is in register 06. 0: Disable 1: Enable CPU Configuration Ready. This bit is set by the AL126 to provide an indication that the register file initialization is completed by the CPU. 0: Not initialized. 1: Register file initialization done. Network Management Enable Control. ...
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... SuperMAC. When this option is selected, the AL126 MAC controller will use a more aggressive back off algorithm. This enables the switch to transmit frame earlier. (Meaningful only in half-duplex mode). 0: Disable. Device will perform the IEEE 802.3 standard exponential back off algorithm when a collision occurs ...
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Table 23: System Configuration Register III (Register 02) BIT NAME 15 SelRMIIP0 14 CPUOffL 13 ClkSel 12 L2T0En 11 L2T1En 10 SlowAge 9 BpIPG64 8 SIPG 7~6 BPRate 5 SG16M 4 BPCOL 10/00 Selects RMII for Port 0. (See Register ...
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Table 23: System Configuration Register III (Register 02) (Continued) 3 ETEnb 2 BebSel 1 PQWRREn 0 FlowCtrlBC Table 24: System Configuration Register IV (Register 03) BIT NAME 15 QEnable 14 AL300AEn 13 GWPrst 12 ALTGW 11 IPMCtrap 10 IGMPtrap 9 ...
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Table 24: System Configuration Register IV (Register 03) (Continued) 7 802Xtrap 6 L2FailEn 5~4 L2Timer 3 D3GigaOn 2 D2GigaOn 1 D1GigaOn 0 D0GigaOn 10/00 Trunking Control Frame Trap Enable. Enables IEEE 802.3ad Port Aggregation MAC Control Frame Trap. 0: Disable ...
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... This register is used to program the vendor specific PHY option also used for programming the Vendor Specific PHY register location and bit location of the operation status. Please refer to the respective 10/100 Fast Ethernet PHY data sheet (in MDIO programming section) connected to the AL126 for appropriate register settings. Table 26: Vendor PHY Operating Mode (Register 05) BIT ...
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... Priority Queue Assignment Register (Register 07) Recommended Setting: 1111 1010 0100 0001 The AL126 allows the tagged priority to be assigned to any of the four priority queues. The AL126 will transmit the frames based on the priority of the queue, not the priority tag. Table 28: Priority Queue Assignment Register (Register 07) ...
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Table 28: Priority Queue Assignment Register (Register 07) (Continued) 3~2 PL1QA 1~0 PL0QA Output Queue Management Register I (Register 08) Recommended Setting: 0011 1111 1111 1111 Table 29: Output Queue Management Register I (Register 08) BIT NAME 15 MaxDrop 14 ...
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... Maximum # of buffer blocks priority queue 3 can hold if both priority queue and output port max limit controls are enabled. The AL126 uses this value to set its own buffer-full status in “Queue Status” registers for each of the output priority queues. When this threshold is reached, “ ...
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Priority Queue Weight Round-Robin Control Register (Register 0A) Recommended Setting: 1111 0111 0011 0001 This register controls the weight of each priority queue, when weight priority queuing is selected. Note: Q3 weight should be bigger or equal to Q2, Q2 ...
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... Disable 1: Enable HiMmode Memory Mode Selection. Selects the Device ID=4, such as the AL3000. Select 0 for devices with one packet memory (such as the AL126 or AL3000), or select 1 for devices with dual packet memory (such as the AL1022). 0: Single buffer. 1: Dual buffers. D3Mmode Memory Mode Selection for the Device ID=3 ...
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Table 33: RoX-II Control Register II (Register 0C) (Continued) BIT 9~5 4~0 Port Configuration Registers I Registers are for local port configuration. There are two port configurations per port. Port 0 port configuration uses register 0D and ...
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Table 34: Port Configuration Registers I (Continued) 7 StormCTL 6 Security 5 LCPUOn 4 LrnDis 3~2 PortST 1~0 Reserved 10/00 Broadcast Storm Control Enable. Global setting in register 2, FlowCtrlBC controls whether this storm control acts on multicast and broadcast, ...
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... PHY will set the PHY capability advertisement register. The link will auto-negotiate to the highest capability. 0111: Selects forced mode. When the AL126 is in this mode, it will turn off auto-negotiation and the PHY will select the link’s operating mode. MDIO Disable. ...
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PrtCfgMode[3:0] BIT NAME 15~8 Dev3Map 7~0 Dev2Map BIT NAME 15~8 Dev1Map 7~0 Dev0Map 10/00 Table 35: Port Configuration Registers II Force Port Operation Mode. Effective only when MDIOCfg is set to master or forced mode, or when MDIODis is ...
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VLAN Map Extension Register I (Register 2D) Recommended Setting: 0000 0000 0000 0000 Table 38: VLAN Map Extension Register I (Register 2D) BIT NAME 15 P7GW7On 14 P6GW7On 13 P5GW7On 12 P4GW7On 11 P3GW7On 10 P2GW7On 9 P1GW7On 8 P0GW7On ...
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Table 39: VLAN Map Extension Register II (Register 2E) BIT NAME 15~8 Reserved 7 P7GW6On 6 P6GW6On 5 P5GW6On 4 P4GW6On 3 P3GW6On 2 P2GW6On 1 P1GW6On 0 P0GW6On Register Group for Port Based Trunking Registers (Registers 2F ~ 36) ...
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Table 40: Trunk Port Assignment Register (2F~36 BIT NAME 15~14 Port7TP 13~12 Port6TP 11~10 Port5TP 9~8 Port4TP 7~6 Port3TP 5~4 Port2TP 3~2 Port1TP 1~0 Port0TP Register Grouping for Layer 2 Trunking (2F~33) Using registers 2F~33 are defined by ...
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Layer 2 Trunking Assignment Register II (Register 30) Recommended Setting: 1111 0000 0000 1111 Table 42: Layer 2 Trunking Assignment Register II (Register 30) BIT NAME 15~8 T3Member 7~0 T2Member Layer 2 Trunking Assignment Register III (Register 31) Recommended Setting: ...
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Layer 2 Trunking Protocol Register (Register 33) Recommended Setting: 0000 0000 0000 0000 Table 45: Layer 2 Trunking Protocol Register (Register 33) BIT NAME 15~14 T7Ptcl 13~12 T6Ptcl 11~10 T5Ptcl 9~8 T4Ptcl 7~6 T3Ptcl 5~4 T2Ptcl 3~2 T1Ptcl 1~0 T0Ptcl ...
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... EEPROM Time Out. 0: EEPROM initializes the device. 1: Device is ready to be programmed by the CPU. 0: Checksum correct. 1: EEPROM checksum error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Network Utilization Indicator Counter. The AL126’ 0011. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 78 ...
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Table 49: Port Operation Status Registers (3A~41) BIT NAME 15 LinkFail 14 PHYError 13 Sviolation 12 FlowCtrl 11 Stormed 10 InBFull 9 TblUNAVL 8 Jabbered 7 LateCOL 6 TxPaused 5 CRSLoss 10/00 DESCRIPTION Port Link Status. 0: Normal 1: Fail ...
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Table 49: Port Operation Status Registers (3A~41) (Continued) 4 FalseCRS 3 Underflow 2 TimeOut 1~0 PortMode Indirect Resource Access Command Register (Register 42) This register is used for managing the resource of the switch. Table 50: Indirect Resource Access Command ...
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Table 50: Indirect Resource Access Command Register (Register 42) (Continued) 10~0 ResAddr Table 51: Indirect Resource Access Data Register I (Register 43) BIT NAME 15~0 IRAData Table 52: Indirect Resource Access Data Register II (Register 44) BIT NAME 15~0 IRAData ...
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... RMON Source and Destination Registers (Registers 48) These registers are used by the RMON Host Group for frame counting. The AL126 supports hardware counter for one host. The RMON manager counts the frames to (destination) and from (source) these MAC addresses stored in the register. ...
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Table 60: Monitored Destination Host Register II (Register 4C) BIT NAME 15~0 DSTMAC[31:16] Table 61: Monitored Destination Host Register III (Register 4D) BIT NAME 15~0 DSTMAC[15:0] Table 62: Default Priority/VLAN Register (Register 4E~6E BIT NAME 15 Reserved 14~12 ...
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Timing Requirements SYMBOL t TXCLK to TXD valid time. tdv t TXCLK to TXEN valid time. txev SYMBOL t TXCLK to TXD valid time. tdv t TXCLK to TXEN valid time. txev Note: Delays are assuming 10pf loading on ...
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SYMBOL t RX_DV, RXD, RX_ER, setup rxds time. t RX_DV, RXD, RX_ER hold time. rxdh SYMBOL t RX_DV, RXD, RX_ER, setup rxds time. t RX_DV, RXD, RX_ER hold time. rxdh RXCLK RXDV RXD Figure 12 RMII/MII Receive Timing Diagram 10/00 ...
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SYMBOL t Setup time. roxs t Hold time. roxh RICLK RID Figure 13 RoX-II Bus Timing Table 70: PHY Management (MDIO) Read Timing SYMBOL t MDC high time MDC low time MDC period MDIO ...
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Table 71: PHY Management (MDIO) Write Timing SYMBOL t MDC high time MDC low time MDC period MDIO setup time MDIO hold time. mh MDC MDIO Figure 15 PHY Management Write Timing ...
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Precharge command period Auto-refresh to auto-refresh period. rc SYMBOL t Access time Access hold time Access setup time PBCS#, PBRAS#, PBWE# hold time Clock high level width. chi t ...
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SYMBOL t Access hold time Access setup time PBCS#, PBRAS#, PBWE# ch hold time. t Clock high level width. chi t System clock cycle time CKE hold time. ckh t CKE setup time. cks ...
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Electrical Specifications Note: Operation at absolute maximum ratings could cause permanent damage to the device. DC Supply Voltage (VDD25) DC Supply Voltage (VDD33) DC Input Voltage DC Output Voltage DC Supply Voltage to MII DC Input Voltage to MII ...
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... AL126 Mechanical Data Figure 16 AL126 Mechanical Dimensions 10/00 Reference Only / Allayer Communications 91 ...
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Appendix I (VLAN Mapping Work Sheet) PORT BIT 10/00 Reference Only / Allayer Communications 92 ...
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Appendix II (Port to Trunk Port Assignment Work Sheet) TRUNK / TRUNK 1 BITS 3, 2 TRUNK 0 BITS 1, 0 10/00 BIT/ PORT VALUE ...
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... Note: This is only a partial list of memory components that can be used in Allayer devices. The AL126 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 100 MHz or faster with CAS latency 2. The AL126 uses MAC Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, 100 MHz or faster ...
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Appendix IV (Memory Timing Requirements) Note: These are the recommended timing requirements for 100 MHz systems. SYMBOL t OE# high to output high-Z. oehz t Data in setup time OE# high to output high-Z + ...
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Revision History Rev. 1.3 (7/18/99) 1. Added memory information in appendix III. Rev. 1.3a (7/28/99) 1. Reformatted layout. 2. Added new PHY management timing diagrams. 3. Added new RMII and MII timing diagrams. Rev. 1.4 (10/8/99) 1. Updated System Performance ...
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... Managed Routing Switch 5 A Address Aging 31 Address Learning 30 AL126 Mechanical Dimensions 91 AL126 Overview 5 AL126 Pin Diagram (Top View) 7 AL126 Pin Lay-out 8 Appendix I (VLAN Mapping Work Sheet) 92 Appendix II (Port to Trunk Port Assignment Work Sheet) 93 Appendix III (Suggested Memory Components) 94 Appendix IV (Memory Timing Requirements) 95 ...
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... Q Queue Management 41 R Read Cycle Timing 47 Recommended Operation Conditions 90 Register Descriptions for the AL126 53 Register Group for Port Based Trunking Registers (Registers 2F ~ 36) 74 Register Grouping for Layer 2 Trunking (2F~33) 75 Reprogramming the EEPROM Configuration 47 Reserved (Register 6F) 83 RMII Receive Timing 85 RMII Transmit Timing 84 ...