AL2100KQT Broadcom Corporation, AL2100KQT Datasheet
AL2100KQT
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AL2100KQT Summary of contents
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Ultra Low-Power 100 Mbps Ethernet Media Converter The AL2100 is designed for media converter applications intended for 100 Mbps Fast ...
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... DATE AL2100-DS00-R 2/22/02 ® Broadcom , the pulse logo, and QAMLink are registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. CHANGE DESCRIPTION Initial Release Broadcom Corporation P.O. Box 57013 ...
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Section 1: Overview............................................................................................................. 1 Section 2: Pin Descriptions ................................................................................................ 2 Section 3: Functional Description...................................................................................... 6 100Base-TX to 100Base-FX Conversion .................................................................................................... 6 100Base-FX to 100Base-TX Conversion .................................................................................................... 6 Full Duplex Application ............................................................................................................................... 6 Elastic Store ................................................................................................................................................. 6 Fault Propagation......................................................................................................................................... 6 ...
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Baseline Wander Correction..................................................................................................................14 Multi mode Transmitter..........................................................................................................................15 Stream Cipher Scrambler/Descrambler.................................................................................................15 HP-Auto MDI/MDIX ...............................................................................................................................15 100Base Fiber PHY .....................................................................................................................................15 Encoder/Decoder...................................................................................................................................15 Link Monitor ...........................................................................................................................................15 Clock Recovery .....................................................................................................................................16 Transmitter ............................................................................................................................................16 Far End Fault (FEF)...............................................................................................................................16 Transmit Driver ......................................................................................................................................16 Section 4: Register Descriptions ..................................................................................... 17 100base-Tx PHY ...
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Power Management Register ............................................................................................................... 30 Operation Mode Register ...................................................................................................................... 30 CRC for Recent Received Packet......................................................................................................... 31 Common Registers .................................................................................................................................... 31 Mode Control Register .......................................................................................................................... 31 Common Register 1, 2, and 3 ............................................................................................................... 31 LED Blink Rate Register 4 .................................................................................................................... ...
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Section 9: TX Application Termination ........................................................................... 44 Section 10: FX Application Termination ......................................................................... 45 Section 11: Power and Ground Filtering......................................................................... 46 Section 12: Package Dimensions (48-Pin TQFP) ........................................................... 47 Section 13: Packaging Thermal Characteristics ............................................................ 48 48-TQFP Package .......................................................................................................................................48 Section ...
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Figure 1: System Block Diagram ..........................................................................................................................i Figure 2: AL2100 Pin Out ................................................................................................................................... 1 Figure 3: State Machine for Redundant Function............................................................................................... 8 Figure 4: Redundant Link ................................................................................................................................... 9 Figure 5: Reset Timing ..................................................................................................................................... 42 Figure 6: Management Interface Timing........................................................................................................... 43 ...
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Bro adco m C orp or atio n 2/22/02 ...
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Table 1: Pin Descriptions.................................................................................................................................... 2 Table 2: LED Formats ...................................................................................................................................... 11 Table 3: Events for LED’s Operation ................................................................................................................ 11 Table 4: SPD100 0 Setting ............................................................................................................................... 13 Table 5: Registers 0 through 31 ....................................................................................................................... 17 Table 6: Register 0: Control ...
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Table 33: Common Register 6: LED0 Setting2 (Map to TP_Phy, Reg. 31, Page 1 a28 [15:12] = 0001)..........32 Table 34: Common Register 7: LED1 Setting1 (Map to TP_Phy, Reg. 29, Page 2 a28 [15:12] = 0010)..........32 Table 35: Common Register ...
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The AL2100 (Figure 2) contains a physical layer interface (PHY) for 100BASE-TX and a PHY for 100BASE-FX networks. The PHY contains all the necessary functions such as elastic store, quantizer, and driver circuits to complete a media converter design. ...
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AL2100 Section 2: Pin Descriptions Signal Types Power pin G = Ground pin AI = Analog Input pin AO = Analog Output pin D = Digital Pull-Down pin U = Digital Pull-Up pin # = Active Low B ...
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PIN Name PIN # RMT_LPBK_DIS/ 14 DATA_OFF TP2FX_DIS/ 15 (Reserved) RMT_LPBK_EN 16 GND 17 VCC 18 PHYAD0/ LED_TP_SD 19 LED0 20 LED1 21 DUPLEX/LED2 22 ANEN/LED3 23 PDOWN# 24 VCC 25 RXN 26 RXP 27 Document AL2100-DS00-R Table 1: ...
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AL2100 PIN Name PIN # SD_A/FXEN_A 28 GND 29 GND 30 RBIAD 31 VCCPLL 32 GND 33 TXN 34 TXP 35 VCC 36 GND 37 GND VCC 41 RST# 42 MDIO 43 MDC 44 PHYAD1/LED_FX_SD ...
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PIN Name PIN # PHYAD3/LED4_FDX 47 PHYAD4/FX_DIS 48 Document AL2100-DS00-R Table 1: Pin Descriptions Type Description BD PHYAD3 (reset-read input): pull high or low to set PHY address bit 3 for serial management functions. LED4_FDX (output): The default behavior ...
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AL2100 Section 3: Functional Description The AL2100 contains a physical layer interface (PHY) for 100BASE-TX, and a PHY for 100BASE-FX networks. The PHY contains all the necessary functions, such as elastic store, quantizer, and driver circuits, to complete a media ...
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IBER TO IBER This is the same as the remote fault function. When remote fault is disabled, the AL2100 disables the FX transmission if the received SD fails IBER TO WISTED AIR ...
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AL2100 R F EDUNDANT UNCTION FAULT_OUT = DATA_ENABLE && !FX_LINK; The logic above uses the TP_RCVR_ACTIVE signal to gate the FX output. When the TP receiver is disconnected, it forces the FX side to drop the link, and causes the ...
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R L EDUNDANT INK The AL2100 supports redundant links through the use of the DATA_OFF and REDUN# signals. The redundant link function is only available for the fiber port. An implementation of a redundant link is shown in Figure ...
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AL2100 RANSMITS INK AULT The 100BASE-FX specification provides a way to detect a transmit-link failure. Whenever a fiber receiver experiences a receive-link failure, it transmits a far-end fault signal. The far-end fault signal is indicated by the ...
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LED I NDICATORS LED Output. . All the LED pins in the AL2100 are multifunction I/Os. Their input is used in the reset-read operation for the secondary definition. All LED pins have internal pull-ups. The ON output value depends ...
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AL2100 LED [5:0] Bit Each LED has two 16-bit registers that define the operation. See ”Common Registers” on page 31 for details ERIAL ANAGEMENT NTERFACE MII management access is performed via pin ...
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P ASE WISTED AIR G D ENERAL ESCRIPTION The twisted pair PHY performs all of the physical layer interface functions for 100Base-TX full or half-duplex on CAT5 twisted pair cable. The 100Base-TX PHY performs encoder/decoder, link monitor, ...
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AL2100 Register Bit Name 0.8 Duplex 4.8/1.14 100Base-TX Full Duplex 4.7/1.13 100Base- NALOG DAPTIVE QUALIZER The analog adaptive equalizer removes inter-symbol interference (ISI) created by the transmission channel media. The PHY is designed to accommodate a maximum ...
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M T ULTI MODE RANSMITTER The multimode transmitter transmits MLT3 coded symbols in100Base-TX mode, NRZI coded symbols in 100Base-FX mode. It uses a current drive output, which is well balanced, and produces very low noise transmit signals. PECL voltage ...
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AL2100 C R LOCK ECOVERY The digital clock recovery creates all internal transmit and receive clocks. The transmit clock is locked to the 25 Mhz clock input, while the receive clock is lock to the incoming data stream. The clock ...
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Section 4: Register Descriptions The first seven registers of the MII register set are defined by the MII specification. In addition to these required registers are several Altima Communications, Inc. specific registers. There are reserved registers and/or bits that ...
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AL2100 Register Description 21 Receive Error Counter Register 22-31 Reserved C R ONTROL EGISTER Register Name Description Bit 0.15 Reset 1 = PHY reset. This bit is self-clearing. 0.14 Loop back 1 = Enable loopback mode. This loops back TXD ...
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S R TATUS EGISTER Register Name Description Bit 1.15 100Base-T4 Permanently tied to 0 indicates no 100BaseT4 capability. 1.14 100Base- 100BaseTX full-duplex capable. Full Duplex 0 = Not 100BaseTX full-duplex capable. 1.13 100Base- 100BaseTX half-duplex ...
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AL2100 PHY DENTIFIER EGISTER Register Name Description Bit 2.[15:0] OUI Composed of the third through the 18th bits of the Organizationally Unique Identifier (OUI), respectively. See Note below. Based on an OUI of 0010A9 (hex) Note PHY ...
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Table 10: Register 4: Auto-Negotiation Advertisement Register Register Name Description Bit 4.10 FDFC Full-Duplex Flow Control 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in Clause ...
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AL2100 Table 11: Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Register Name Description Bit 5.[4:0] Selector Field Protocol Selection [00001] = IEEE 802.3. When this register is used as Next Page Message, the bit definition is ...
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Table 13: Register 7: Auto-Negotiation Next Page Transmit Register Register Name Description Bit 7.12 ACK2 1 = Complies with message Does not comply with message. 7.11 TOG_TX 1 = Previous value of transmitted link code word equals ...
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AL2100 Table 15: Register 19: Power/Loopback Register Register Name Description Bit 19.5 Disable watch 1 = Disable watchdog timer. dog timer for 0 = Enable watchdog timer. decipher 19.4 Low Power 1= Disable advance power saving mode. Mode disable 0= ...
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ECEIVE RROR OUNTER Register Name Description Bit 21.[15:0] RX_ER Count receive error events. Counter OWER ANAGEMENT EGISTER Table 18: Register 22: Power Management Register Register Name Description Bit 22.[15:14 Reserved ] 22.13 PD_PLL ...
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AL2100 Table 19: Register 23: Operation Mode Register Register Name Description Bit 23.11 Scramble 1 = Disable scrambler data. disable 0 = Enable scrambler data. 23.10 Reserved 23.9 Pcsbp 1 = Enable PCS bypass mode disable PCS bypass ...
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PHY R ASE EGISTERS Register Name 0 Control Register 1 Status Register 2 PHY Identifier 1 Register 3 PHY Identifier 2 Register 4-20 Reserved 21 Receive Error Counter Register 22-31 Reserved C R ONTROL EGISTER Register Bit ...
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AL2100 Register Bit Name 0.7 Collision Test 0.[6:0] Reserved S R TATUS EGISTER Register Bit Name 1.15 100Base-T4 1.14 100Base-TX Full Duplex 1.13 100Base-TX Half Duplex 1.12 10Base-T Full Duplex 1.11 10Base-T Half Duplex 1.[10:7] Reserved 1.6 MF Preamble Suppression ...
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Register Bit Name 1.0 Extended Capability PHY DENTIFIER EGISTER Register Bit Name 2.[15:0] OUI* Based on an OUI is 0010A9 (hex). Note PHY DENTIFIER EGISTER Register Bit Name 3.[15:10] OUI 3.[9:4] Model Number ...
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AL2100 OWER ANAGEMENT EGISTER Table 27: Register 22: Power Management Register Register Bit Name 22.[15:14] Reserved 22.13 PD_PLL 22.12 PD_EQUAL 22.11 Reserved 22.10 PD_LP 22.9 PD_EN_DET 22.8 PD_FX 22.[7:6] Reserved 22.5 MSK_PLL 22.4 MSK_EQUAL 22.3 Reserved 22.2 ...
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Table 28: Register 23: Operation Mode Register Register Bit Name 23.[4:0] Reserved CRC R R FOR ECENT ECEIVED Table 29: Register 24: CRC for Recent Received Packet Register Name Bit 24.[15:0] CRC16 C R OMMON EGISTERS The following registers ...
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AL2100 LED LINK ATE EGISTER Table 31: Common Register 4: LED Blink Rate (Map to TP_Phy, Reg. 29, Page 1 a28 [15:12] = 0001) Register Bit Name A1.29 [15:8] Reserved A1.29.[7:0] Blink Rate LED0 ...
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Table 34: Common Register 7: LED1 Setting1 (Map to TP_Phy, Reg. 29, Page 2 a28 [15:12] = 0010) Register Bit Name A2.29.8 Force LED Off A2.29.[7:0] Msk Blink LED1 ETTING EGISTER Table 35: Common Register ...
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AL2100 LED3 ETTING EGISTER The default operation for LED3 FX_LINK, BLINK on Remote_fault. Table 38: Common Register 11: LED3 Setting1 (Map to TP_Phy, Reg. 30, Page 3 a28 [15:12] = 0011) Register Bit ...
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LED4 ETTING EGISTER Table 41: Common Register 14: LED4 Setting2 (Map TP_Phy, Reg 30, Page 4 a28[15:12] = 0100) Register Bit Name A4.30. Msk On [15:8] A4.30.[7:0] Msk Off LED5 ETTING ...
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AL2100 Table 44: Common Register 17: Configuration Pin State Register Register Bit Name 12 FX2TP_DIS 11 TP2FX_DIS 10 Reserved 9 PHYAD0 8 Reserved 7 Reserved 6 DUPLEX 5 ANEN 4 PHYAD4 3 PHYAD3 2 PHYAD2 1 PHYAD1 0 Reserved Page ...
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Section 5: 4B/5B Code-Group Table Symbol Name 4B Code 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 ...
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AL2100 Symbol Name 4B Code V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined Page 38 Section 5: 4B/5B Code-Group Table Table 45: 4B/5B Code-Group Table 5B Code Description 00001 Invalid ...
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Section 6: SMI Read/Write Sequence Preamble Start (32 Bits) (2 Bits) Read 1…1 01 Write 1…1 01 Document AL2100-DS00-R Table 46: SMI Read/Write Sequence OpCode PHYAD REGAD (2 Bits) (5 Bits) (5 Bits) 10 AAAAA RRRRR 01 AAAAA RRRRR ...
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AL2100 Section 7: Electrical Specifications NOTE: The following electrical characteristics are design goals rather than characterized numbers BSOLUTE AXIMUM RATINGS Parameter SUPPLY VOLTAGE Input Voltage Input Current Supply to AL2100 Storage Temperature Electrostatic Discharge R O ECOMMENDED PERATING ...
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E C LECTRICAL HARACTERISTICS Parameter Symbol Supply Current I CC Supply Current Power I CC Down Mode High-Level Output V OH Voltage High-Level Output V OH Voltage Low-Level Output V OL Voltage Low-Level Output V OL Voltage Differential Output ...
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AL2100 Section 8: Timing and AC Characteristics C T LOCK IMING Parameter XTAL Input Cycle Time XTAL Input High/Low Time XTAL Input Rise/Fall Time R T ESET IMING Parameter Reset Pulse Length Low Period with Stable XTAL Input Reset Rise/Fall ...
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Parameter MDC Cycle Time MDC High/Low MDC Rise/Fall Time MDIO Input Setup Time to MDC Rising MDIO Input Hold Time from MDC Rising MDIO Output Delay from MDC Rising MDC MDIO (into AL2100) MDIO (from AL2100) Document AL2100-DS00-R Table ...
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AL2100 Section 9: TX Application Termination TXP TXN AL2100 RXP RXN Auto MDI/MDIX Magnetics: BEL: S558-5999-WD; Pulse: H1102; HALO: TG110-S050n2 Page 44 Section 9: TX Application Termination 2.5V Auto MDI/MDIX Magnetic 2.5V Figure 7: TX Application Bro adco m C ...
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Section 10: FX Application Termination Please contact Altima Communications, Inc. for the latest component value recommendation. 3_3V FIP FIN AL2100 SD/FXEN_B FOP FON C12 1UF Document AL2100-DS00-R 2_5V 3_3V C8 .1uF Z=50 Ohm C9 .1uF Z=50 Ohm Z=50 Ohm ...
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AL2100 Section 11: Power and Ground Filtering Place the capacitor as close as possible to each power pin. Page 46 Section 11: Power and Ground Filtering Power Connections for AL2100 AL2100 VCCPLL VCC VCC .01UF 2.2UF .1UF .1UF .1UF .1UF ...
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Section 12: Package Dimensions (48-Pin TQFP) Document AL2100-DS00-R Figure 10: Quad Flat Pack Outline ( mm) Bro adco atio n Section 12: Package Dimensions (48-Pin TQFP) Page 47 ...
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AL2100 Section 13: Packaging Thermal Characteristics 48-TQFP P ACKAGE Table 53: 48-TQFP Package Thermal Characteristics Airflow (Feet/Minute 0 53.9 °C/W Theta JA (°C/W) Maximum Junction Temperature Theta JC (°C/W) at Max Junction Temperature of 125 °C Page 48 Section 13: ...
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... Section 14: Ordering Information Part Number AL2100KQT Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others ...