AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 21

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058KS–AVR32–01/12
9. Memories
9.1
9.2
Table 9-1.
Device
Embedded SRAM
Embedded Flash
EBI SRAM CS0
EBI SRAM CS2
EBI SRAM CS3
EBI SRAM CS1
/SDRAM CS0
USB
Configuration
HSB-PB Bridge A
HSB-PB Bridge B
Embedded Memories
Physical Memory Map
AT32UC3A Physical Memory Map
Start Address
0x0000_0000
0x8000_0000
0xC000_0000
0xC800_0000
0xCC00_0000
0xD000_0000
0xE000_0000
0xFFFE_0000
0xFFFF_0000
•
•
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Internal High-Speed Flash
Internal High-Speed SRAM, Single-cycle access at full speed
– 512 KBytes (AT32UC3A0512, AT32UC3A1512)
– 256 KBytes (AT32UC3A0256, AT32UC3A1256)
– 128 KBytes (AT32UC3A1128, AT32UC3A2128)
– 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256)
– 32KBytes (AT32UC3A1128)
- 0 Wait State Access at up to 33 MHz in Worst Case Conditions
- 1 Wait State Access at up to 66 MHz in Worst Case Conditions
- Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
- Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
- 100 000 Write Cycles, 15-year Data Retention Capability
- 4 ms Page Programming Time, 8 ms Chip Erase Time
- Sector Lock Capabilities, Bootloader Protection, Security Bit
- 32 Fuses, Erased During Chip Erase
- User Page For Data To Be Preserved During Chip Erase
Size
AT32UC3A0512
64 Kbyte
512 Kbyte
16 Mbyte
16 Mbyte
16 Mbyte
128 Mbyte
64 Kbyte
64 Kbyte
64 Kbyte
AT32UC3A1512
64 Kbyte
512 Kbyte
-
-
-
-
64 Kbyte
64 Kbyte
64 Kbyte
AT32UC3A0256
64 Kbyte
256 Kbyte
16 Mbyte
16 Mbyte
16 Mbyte
128 Mbyte
64 Kbyte
64 Kbyte
64 kByte
AT32UC3A1256
64 Kbyte
256 Kbyte
-
-
-
-
64 Kbyte
64 Kbyte
64 kByte
AT32UC3A0128
32 Kbyte
128 Kbyte
16 Mbyte
16 Mbyte
16 Mbyte
128 Mbyte
64 Kbyte
64 Kbyte
64 Kbyte
AT32UC3A
AT32UC3A1128
32 Kbyte
128 Kbyte
-
-
-
-
64 Kbyte
64 Kbyte
64 Kbyte
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