AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 82

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058KS–AVR32–01/12
15.4.6
15.4.7
15.4.8
15.4.9
15.4.10
15.4.11
PDCA
TWI
SDRAMC
GPIO
USART
Processor and Architecture
1. Wrong PDCA behavior when using two PDCA channels with the same PID.
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.
1.
1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant
1. ISO7816 info register US_NER cannot be read
1. LDM instruction with PC in the register list and without ++ increments Rp
2. RETE instruction does not clear SREG[L] from interrupts.
3.
(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to
an exception or to other errors derived from this corrupted read access.
Fix/Workaround
Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or
through the EBI. After these commands, read twice one flash page initialized to 00h in each
half part of the flash.
Workaround/fix
The same PID should not be assigned to more than one channel.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
Code execution from SDRAM does not work.
Fix/Workaround
Do not run code from SDRAM.
Only 11 GPIOs remain 5V tolerant (VIHmax=5V):PB01, PB02, PB03, PB10, PB19, PB20,
PB21, PB22, PB23, PB27, PB28.
Workaround/fix
None.
The NER register always returns zero.
Fix/Workaround
None.
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
Code execution from external SDRAM does not work
Exceptions when system stack is protected by MPU
AT32UC3A
82