AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 90

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058KS–AVR32–01/12
15.5.9
15.5.10
HMatrix
ADC
4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz.
5.
6.
7. If the BOD level is higher than VDDCORE, the part is constantly under reset
8. System Timer mask (Bit 16) of the PM CPUMASK register is not available.
1. HMatrix fixed priority arbitration does not work
1.
2.
3. Sleep Mode activation needs additional A to D conversion
Fix/Workaround
In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour.
Fix/Workaround
Do not set PBA frequency higher than 33 MHz.
In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators.
This can cause drive contention on the XINx in worst case.
Fix/Workaround
Before entering stop mode set all PCx pins to input and GPIO controlled.
Fix/Workaround
Do not set the HSB/CPU speed higher than 50MHz when the firmware generate exceptions.
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
Fix/Workaround
Do not use this bit.
Fixed priority arbitration does not work.
Fix/Workaround
Use Round-Robin arbitration instead.
The ADC does not work properly when more than one channel is enabled.
Fix/Workaround
Do not use the ADC with more than one channel enabled at a time.
The OVRE flag does not clear properly if read simultaneously to an end of conversion.
Fix/Workaround
None.
PCx pins go low in stop mode
On some rare parts, the maximum HSB and CPU speed is 50MHz instead of 66MHz.
ADC possible miss on DRDY when disabling a channel
ADC OVRE flag sometimes not reset on Status Register read
AT32UC3A
90