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AT32UC3C0128C
AT32UC3C0128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C0128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C0128C datasheets |
|
Availability: In stock
International delivery:
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Specifications of AT32UC3C0128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
9.3.11
Coprocessor interface
Table 9-13.
Coprocessor Interface
Mnemonics
Operands / Syntax
CP#, CRd, CRx,
cop
E
CRy, Op
E
CP#, CRd, Rp[disp]
E
CP#, CRd, --Rp
ldc.d
CP#, CRd,
E
Rb[Ri<<sa]
ldc0.d
E
CRd, Rp[disp]
E
CP#, CRd, Rp[disp]
E
CP#, CRd, --Rp
ldc.w
CP#, CRd,
E
Rb[Ri<<sa]
ldc0.w
E
CRd, Rp[disp]
CP#, Rp{++},
ldcm.d
E
ReglistCPD8
CP#, Rp{++},
ldcm.w
E
ReglistCPH8
CP#, Rp{++},
ldcm.w
E
ReglistCPL8
mvcr.d
E
CP#, Rd, CRs
mvcr.w
E
CP#, Rd, CRs
mvrc.d
E
CP#, CRd, Rs
mvrc.w
E
CP#, CRd, Rs
E
CP#, Rp[disp], CRs
E
CP#, Rp++, CRs
stc.d
CP#, Rb[Ri<<sa],
E
CRs
stc0.d
E
Rp[disp], CRs
E
CP#, Rp[disp], CRs
E
CP#, Rp++, CRs
stc.w
CP#, Rb[Ri<<sa],
E
CRs
stc0.d
E
Rp[disp], CRs
32000D–04/2011
Description
Coprocessor operation.
Load coprocessor register
Load coprocessor register with pre-
decrement
Load coprocessor register with indexed
addressing
Load coprocessor 0 register
Load coprocessor register
Load coprocessor register with pre-
decrement
Load coprocessor register with indexed
addressing
Load coprocessor 0 register
Load multiple coprocessor double
registers
Load multiple coprocessor high
registers
Load multiple coprocessor low registers
Move from coprocessor to register
Move from coprocessor to register
Move from register to coprocessor
Move from register to coprocessor
Store coprocessor register
Store coprocessor register with post-
increment
Store coprocessor register with indexed
addressing
Store coprocessor 0 register
Store coprocessor register
Store coprocessor register with post-
increment
Store coprocessor register with indexed
addressing
Store coprocessor 0 register
AVR32
Operation
CRd ← CRx Op CRy
CRd+1:CRd ← *(Rp+ZE(disp8<<2))
CRd+1:CRd ← *(--Rp)
CRd+1:CRd ← *(Rb+(Ri << sa2))
CRd+1:CRd ← *(Rp+ZE(disp12<<2))
CRd ← *(Rp+ZE(disp8<<2))
CRd ← *(--Rp)
CRd ← *(Rb+(Ri << sa2))
CRd ← *(Rp+ZE(disp12<<2))
See instruction set reference
See instruction set reference
See instruction set reference
Rd+1:Rd ← CRs+1:CRs
Rd ← CRs
CRd+1:CRd ← Rs+1:Rs
CRd ← Rs
*(Rp+ZE(disp8<<2)) ← CRs+1:CRs
*(Rp--) ← CRs+1:CRs
*(Rb+(Ri << sa2)) ← CRs+1:CRs
*(Rp+ZE(disp12<<2)) ← CRs+1:CRs
*(Rp+ZE(disp8<<2)) ← CRs
*(Rp++) ← CRs
*(Rb+(Ri << sa2)) ← CRs
*(Rp+ZE(disp12<<2)) ← CRs
Rev
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