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AT32UC3C0128C
AT32UC3C0128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C0128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C0128C datasheets |
|
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Specifications of AT32UC3C0128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
MFSR – Move from System Register
Architecture revision:
Architecture revision1 and higher.
Description
The instruction copies the value in the specified system register to the specified register in the
register file. Note that special timing concerns must be considered when operating on the sys-
tem registers, see the Pipeline Chapter for details.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
31
1
15
0
Note:
Some system registers are implementation defined. If accessing a system register that does not
exist, the result is UNDEFINED.
With the exception of accessing the JECR and JOSP system registers, this instruction can only
be executed in a privileged mode. Execution from any other mode will trigger a Privilege Viola-
tion exception.
JECR and JOSP can be accessed from all modes with this instruction.
32000D–04/2011
Rd ← SystemRegister[SystemRegisterAddress << 2];
mfsr
Rd, SystemRegisterAddress
SystemRegisterAddress ∈ {0, 4, 8, ..., 1020}
Q:
Not affected.
V:
Not affected.
N:
Not affected.
Z:
Not affected.
C:
Not affected.
1
1
0
0
0
0
0
0
0
0
0
0
20
19
1
1
0
1
1
8
7
0
System Register Ad-
AVR32
16
Rd
0
221
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