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AT32UC3C0128C
AT32UC3C0128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C0128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C0128C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of AT32UC3C0128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
PLSL.{B/H} – Packed Logical Shift Left
Architecture revision:
Architecture revision1 and higher.
Description
Perform a logical shift left on each of the packed bytes or halfwords in the source register and
store the result to the destination register.
Operation:
I.
II.
Syntax:
I.
II.
Operands:
I, II.
I.
II.
Status Flags:
Opcode:
31
1
15
0
32000D–04/2011
Rd[31:24] ← LSL(Rs[31:24], sa3);
Rd[23:16] ← LSL(Rs[23:16], sa3);
Rd[15:8] ← LSL(Rs[15:8], sa3);
Rd[7:0] ← LSL(Rs[7:0], sa3);
Rd[31:16] ← LSL(Rs[31:16], sa4);
Rd[15:0] ← LSL(Rs[15:0], sa4);
plsl.b
Rd, Rs, sa
plsl.h
Rd, Rs, sa
{d, s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 7}
sa ∈ {0, 1, …, 15}
Q:
Not affected.
V:
Not affected.
N:
Not affected.
Z:
Not affected.
C:
Not affected.
Format I:
29
28
25
1
1
Rs
0
1
0
0
1
0
24
19
0
0
0
0
0
0
4
3
0
0
0
1
0
AVR32
18
16
sa3
0
Rd
273
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