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AT32UC3C0128C
AT32UC3C0128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C0128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C0128C datasheets |
|
Availability: In stock
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Specifications of AT32UC3C0128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
8.4
Event priority
Several instructions may be in the pipeline at the same time, and several events may be issued
in each pipeline stage. This implies that several pending exceptions may be in the pipeline
simultaneously. Priorities must therefore be imposed, ensuring that the correct event is serviced
first. The priority scheme obeys the following rules:
1. If several instructions trigger events, the instruction furthest down the pipeline is ser-
viced first, even if upstream instructions have pending events of higher priority.
2. If this instruction has several pending events, the event with the highest priority is ser-
viced first. After this event has been serviced, all pending events are cleared and the
instruction is restarted.
Details about the timing of events is IMPLEMENTATION DEFINED, and given in the hardware
manual for the specific implementation.
8.5
Event handling in secure state
Interrupt and exception handling in AVR32A and AVR32B has been described in the previous
chapters. This behavior is modified in the following way when interrupts and exceptions are
received in secure state:
• A sscall instruction will set SR[GM]. In secure state, SR[GM] masks both INT0-INT3, and
NMI. Clearing SR[GM], INT0-INT3 and NMI will remove the mask of these event sources.
INT0-INT3 are still additionally masked by the I0M-I3M bits in the status register.
• sscall has handler address at offset 0x4 relative to the reset handler address.
• Exceptions have a handler address at offset 0x8 relative to the reset handler address.
• NMI has a handler address at offset 0xC relative to the reset handler address.
• BREAKPOINT has a handler address at offset 0x10 relative to the reset handler address.
• INT0-INT3 are not autovectored, but have a common handler address at offset 0x14 relative
to the reset handler address.
Note that in the secure state, all exception sources share the same handler address. It is there-
fore not possible to separate different exception causes when in the secure world. The secure
world system must be designed to support this, the most obvious solution is to design the secure
software so that exceptions will not arise.
AVR32
92
32000D–04/2011
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