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AT32UC3C0512CAU
AT32UC3C0512CAU | |
|---|---|
| Manufacturer Part Number | AT32UC3C0512CAU |
| Manufacturer | Atmel Corporation |
| AT32UC3C0512CAU datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of AT32UC3C0512CAU | |||
|---|---|---|---|
| Flash (kbytes) | 512 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| # Of Touch Channels | 32 | Hardware Qtouch Acquisition | No |
| Max I/o Pins | 123 | Ext Interrupts | 144 |
| Usb Transceiver | 1 | Quadrature Decoder Channels | 2 |
| Usb Speed | Full Speed | Usb Interface | Device + OTG |
| Spi | 7 | Twi (i2c) | 3 |
| Uart | 5 | Can | 2 |
| Lin | 5 | Ssc | 1 |
| Ethernet | 1 | Graphic Lcd | No |
| Video Decoder | No | Camera Interface | No |
| Adc Channels | 16 | Adc Resolution (bits) | 12 |
| Adc Speed (ksps) | 2000 | Analog Comparators | 4 |
| Resistive Touch Screen | No | Dac Channels | 4 |
| Dac Resolution (bits) | 12 | Temp. Sensor | No |
| Crypto Engine | No | Sram (kbytes) | 68 |
| Self Program Memory | YES | External Bus Interface | 1 |
| Dram Memory | sdram | Nand Interface | No |
| Picopower | No | Temp. Range (deg C) | -40 to 85 |
| I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 | Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 |
| Fpu | Yes | Mpu / Mmu | Yes / No |
| Timers | 6 | Output Compare Channels | 22 |
| Input Capture Channels | 12 | Pwm Channels | 20 |
| 32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3A0128AU PDF datasheet #3AT32UC3C0128C PDF datasheet #4AT32UC3C0128C PDF datasheet #5
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Figure 4-1.
Instruction memory controller
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 28
32117CS–AVR-08/11
Overview of the AVR32UC CPU
OCD
system
AVR32UC CPU pipeline
High Speed
High Speed Bus master
shows an overview of the AVR32UC pipeline stages.
AT32UC3C
Power/
Reset
control
MPU
Data memory controller
High
CPU Local
Speed
Bus
Bus master
Bus slave
master
CPU RAM
27
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