AT32UC3C0512CAU

Manufacturer Part NumberAT32UC3C0512CAU
ManufacturerAtmel Corporation
AT32UC3C0512CAU datasheets

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Specifications of AT32UC3C0512CAU

Flash (kbytes)512 KbytesPin Count144
Max. Operating Frequency66 MHzCpu32-bit AVR
# Of Touch Channels32Hardware Qtouch AcquisitionNo
Max I/o Pins123Ext Interrupts144
Usb Transceiver1Quadrature Decoder Channels2
Usb SpeedFull SpeedUsb InterfaceDevice + OTG
Spi7Twi (i2c)3
Uart5Can2
Lin5Ssc1
Ethernet1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels16Adc Resolution (bits)12
Adc Speed (ksps)2000Analog Comparators4
Resistive Touch ScreenNoDac Channels4
Dac Resolution (bits)12Temp. SensorNo
Crypto EngineNoSram (kbytes)68
Self Program MemoryYESExternal Bus Interface1
Dram MemorysdramNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class3.0 to 3.6 or 4.5 to 5.5Operating Voltage (vcc)3.0 to 3.6 or 4.5 to 5.5
FpuYesMpu / MmuYes / No
Timers6Output Compare Channels22
Input Capture Channels12Pwm Channels20
32khz RtcYesCalibrated Rc OscillatorYes
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AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3A0128AU PDF datasheet #3AT32UC3C0128C PDF datasheet #4AT32UC3C0128C PDF datasheet #5
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Page 36/108

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4.5.3
Supervisor Calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
4.5.4
Debug Requests
The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the
Debug Exception handler. By default, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to the previous context.
4.5.5
Entry Points for Events
Several different event handler entry points exist. In AVR32UC, the reset address is
0x80000000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All interrupt requests have entry points located at an offset relative to EVBA. This autovector off-
set is specified by an interrupt controller. The programmer must make sure that none of the
autovector offsets interfere with the placement of other code. The autovector offset has 14
address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on the same instruction, they are handled in a prioritized way. The priority
ordering is presented in
locations in the pipeline, the events on the oldest instruction are always handled before any
events on any younger instruction, even if the younger instruction has events of higher priority
32117CS–AVR-08/11
Table 4-4 on page
38. If events occur on several instructions at different
AT32UC3C
36

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