AT32UC3C0512CAU

Manufacturer Part NumberAT32UC3C0512CAU
ManufacturerAtmel Corporation
AT32UC3C0512CAU datasheets

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Specifications of AT32UC3C0512CAU

Flash (kbytes)512 KbytesPin Count144
Max. Operating Frequency66 MHzCpu32-bit AVR
# Of Touch Channels32Hardware Qtouch AcquisitionNo
Max I/o Pins123Ext Interrupts144
Usb Transceiver1Quadrature Decoder Channels2
Usb SpeedFull SpeedUsb InterfaceDevice + OTG
Spi7Twi (i2c)3
Uart5Can2
Lin5Ssc1
Ethernet1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels16Adc Resolution (bits)12
Adc Speed (ksps)2000Analog Comparators4
Resistive Touch ScreenNoDac Channels4
Dac Resolution (bits)12Temp. SensorNo
Crypto EngineNoSram (kbytes)68
Self Program MemoryYESExternal Bus Interface1
Dram MemorysdramNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class3.0 to 3.6 or 4.5 to 5.5Operating Voltage (vcc)3.0 to 3.6 or 4.5 to 5.5
FpuYesMpu / MmuYes / No
Timers6Output Compare Channels22
Input Capture Channels12Pwm Channels20
32khz RtcYesCalibrated Rc OscillatorYes
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Table 7-34.
ADC and S/H Transfer Characteristics (Continued)12-bit Resolution Mode and S/H gain = 1
Symbol
Parameter
RES
Resolution
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Offset error
Gain error
Note:
1. The measures are done without any I/O activity on VDDANA/GNDANA power domain.
Table 7-35.
ADC and S/H Transfer Characteristics 12-bit Resolution Mode and S/H gain from 1 to 8
Symbol
Parameter
RES
Resolution
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Offset error
Gain error
RES
Resolution
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Offset error
Gain error
Note:
1. The measures are done without any I/O activity on VDDANA/GNDANA power domain
Table 7-36.
ADC and S/H Transfer Characteristics 10-bit Resolution Mode and S/H gain from 1 to 16
Symbol
Parameter
RES
Resolution
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Offset error
Gain error
RES
Resolution
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Offset error
Gain error
Note:
1. The measures are done without any I/O activity on VDDANA/GNDANA power domain.
32117CS–AVR-08/11
Conditions
Differential mode,
V
= 5V,
VDDANA
V
= 3V,
ADCREF0
ADCFIA.SEQCFGn.SRES = 0,
S/H gain = 1
(F
= 1.5MHz)
adc
Conditions
Differential mode,
V
= 3V,
VDDANA
V
= 1V,
ADCREF0
ADCFIA.SEQCFGn.SRES = 0,
S/H gain from 1 to 8
(F
= 1.2MHz)
adc
Differential mode,
V
= 5V,
VDDANA
V
= 3V,
ADCREF0
ADCFIA.SEQCFGn.SRES = 0,
S/H gain from 1 to 8
(F
= 1.5MHz)
adc
Conditions
Differential mode,
V
= 3V,
VDDANA
V
= 1V,
ADCREF0
ADCFIA.SEQCFGn.SRES = 1,
S/H gain from 1 to 16
(F
= 1.5MHz)
adc
Differential mode,
V
= 5V,
VDDANA
V
= 3V,
ADCREF0
ADCFIA.SEQCFGn.SRES = 1,
S/H gain from 1 to 16
(F
= 1.5MHz)
adc
AT32UC3C
(1)
Min
Typ
Max
Units
12
Bit
5
LSB
3
LSB
-10
10
mV
-20
20
mV
(1)
Min
Typ
Max
Units
12
Bit
25
LSB
25
LSB
-10
10
mV
-20
20
mV
12
Bit
9
LSB
10
LSB
-15
15
mV
-20
20
mV
(1)
Min
Typ
Max
Units
10
Bit
3
LSB
3
LSB
-15
15
mV
-20
20
mV
10
Bit
1.5
LSB
1.5
LSB
-25
25
mV
-15
15
mV
66