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AT32UC3C0512CAU
AT32UC3C0512CAU | |
|---|---|
| Manufacturer Part Number | AT32UC3C0512CAU |
| Manufacturer | Atmel Corporation |
| AT32UC3C0512CAU datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of AT32UC3C0512CAU | |||
|---|---|---|---|
| Flash (kbytes) | 512 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| # Of Touch Channels | 32 | Hardware Qtouch Acquisition | No |
| Max I/o Pins | 123 | Ext Interrupts | 144 |
| Usb Transceiver | 1 | Quadrature Decoder Channels | 2 |
| Usb Speed | Full Speed | Usb Interface | Device + OTG |
| Spi | 7 | Twi (i2c) | 3 |
| Uart | 5 | Can | 2 |
| Lin | 5 | Ssc | 1 |
| Ethernet | 1 | Graphic Lcd | No |
| Video Decoder | No | Camera Interface | No |
| Adc Channels | 16 | Adc Resolution (bits) | 12 |
| Adc Speed (ksps) | 2000 | Analog Comparators | 4 |
| Resistive Touch Screen | No | Dac Channels | 4 |
| Dac Resolution (bits) | 12 | Temp. Sensor | No |
| Crypto Engine | No | Sram (kbytes) | 68 |
| Self Program Memory | YES | External Bus Interface | 1 |
| Dram Memory | sdram | Nand Interface | No |
| Picopower | No | Temp. Range (deg C) | -40 to 85 |
| I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 | Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 |
| Fpu | Yes | Mpu / Mmu | Yes / No |
| Timers | 6 | Output Compare Channels | 22 |
| Input Capture Channels | 12 | Pwm Channels | 20 |
| 32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3A0128AU PDF datasheet #3AT32UC3C0128C PDF datasheet #4AT32UC3C0128C PDF datasheet #5
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PrevNext
7.9.7
EBI Timings
See EBI I/O lines description for more details.
Table 7-52.
SMC Clock Signal.
Symbol
Parameter
1/(t
)
SMC Controller clock frequency
CPSMC
Note:
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Table 7-53.
SMC Read Signals with Hold Settings
Symbol
Parameter
SMC
Data setup before NRD high
1
SMC
Data hold after NRD high
2
SMC
NRD high to NBS0/A0 change
3
SMC
NRD high to NBS1 change
4
SMC
NRD high to NBS2/A1 change
5
SMC
NRD high to A2 - A25 change
7
SMC
NRD high to NCS inactive
8
SMC
NRD pulse width
9
SMC
Data setup before NCS high
10
SMC
Data hold after NCS high
11
SMC
NCS high to NBS0/A0 change
12
SMC
NCS high to NBS0/A0 change
13
SMC
NCS high to NBS2/A1 change
14
SMC
NCS high to A2 - A25 change
16
SMC
NCS high to NRD inactive
17
SMC
NCS pulse width
18
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
32117CS–AVR-08/11
(1)
Conditions
NRD Controlled (READ_MODE = 1)
(2)
V
= 3.0V,
VDD
drive strength of the
(2)
pads set to the lowest,
(2)
external capacitor =
40pF
(2)
(2)
NRD Controlled (READ_MODE = 0)
(2)
V
= 3.0V,
VDD
(2)
drive strength of the
pads set to the lowest,
(2)
external capacitor =
(2)
40pF
(2)
AT32UC3C
(1)
Max
f
cpu
Min
32.5
0
nrd hold length * t
- 1.5
CPSMC
nrd hold length * t
- 0
CPSMC
nrd hold length * t
- 0
CPSMC
nrd hold length * t
- 5.6
CPSMC
(nrd hold length - ncs rd hold length) *
t
- 1.3
CPSMC
nrd pulse length * t
- 0.6
CPSMC
34.1
0
ncs rd hold length * t
- 3
CPSMC
ncs rd hold length * t
- 2
CPSMC
ncs rd hold length * t
- 1.1
CPSMC
ncs rd hold length * t
- 7.2
CPSMC
(ncs rd hold length - nrd hold length) *
t
- 2.2
CPSMC
ncs rd pulse length * t
- 3
CPSMC
Units
MHz
Units
ns
ns
81
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