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AT32UC3C0512CAU
AT32UC3C0512CAU | |
|---|---|
| Manufacturer Part Number | AT32UC3C0512CAU |
| Manufacturer | Atmel Corporation |
| AT32UC3C0512CAU datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of AT32UC3C0512CAU | |||
|---|---|---|---|
| Flash (kbytes) | 512 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| # Of Touch Channels | 32 | Hardware Qtouch Acquisition | No |
| Max I/o Pins | 123 | Ext Interrupts | 144 |
| Usb Transceiver | 1 | Quadrature Decoder Channels | 2 |
| Usb Speed | Full Speed | Usb Interface | Device + OTG |
| Spi | 7 | Twi (i2c) | 3 |
| Uart | 5 | Can | 2 |
| Lin | 5 | Ssc | 1 |
| Ethernet | 1 | Graphic Lcd | No |
| Video Decoder | No | Camera Interface | No |
| Adc Channels | 16 | Adc Resolution (bits) | 12 |
| Adc Speed (ksps) | 2000 | Analog Comparators | 4 |
| Resistive Touch Screen | No | Dac Channels | 4 |
| Dac Resolution (bits) | 12 | Temp. Sensor | No |
| Crypto Engine | No | Sram (kbytes) | 68 |
| Self Program Memory | YES | External Bus Interface | 1 |
| Dram Memory | sdram | Nand Interface | No |
| Picopower | No | Temp. Range (deg C) | -40 to 85 |
| I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 | Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 |
| Fpu | Yes | Mpu / Mmu | Yes / No |
| Timers | 6 | Output Compare Channels | 22 |
| Input Capture Channels | 12 | Pwm Channels | 20 |
| 32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3A0128AU PDF datasheet #3AT32UC3C0128C PDF datasheet #4AT32UC3C0128C PDF datasheet #5
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(1)
Table 7-58.
SDRAM Signal
Symbol
Parameter
SDRAMC
SDCKE high before SDCK rising edge
1
SDRAMC
SDCKE low after SDCK rising edge
2
SDRAMC
SDCKE low before SDCK rising edge
3
SDRAMC
SDCKE high after SDCK rising edge
4
SDRAMC
SDCS low before SDCK rising edge
5
SDRAMC
SDCS high after SDCK rising edge
6
SDRAMC
RAS low before SDCK rising edge
7
SDRAMC
RAS high after SDCK rising edge
8
SDRAMC
SDA10 change before SDCK rising edge
9
SDRAMC
SDA10 change after SDCK rising edge
10
SDRAMC
Address change before SDCK rising edge
11
SDRAMC
Address change after SDCK rising edge
12
SDRAMC
Bank change before SDCK rising edge
13
SDRAMC
Bank change after SDCK rising edge
14
SDRAMC
CAS low before SDCK rising edge
15
SDRAMC
CAS high after SDCK rising edge
16
SDRAMC
DQM change before SDCK rising edge
17
SDRAMC
DQM change after SDCK rising edge
18
SDRAMC
D0-D15 in setup before SDCK rising edge
19
SDRAMC
D0-D15 in hold after SDCK rising edge
20
SDRAMC
SDWE low before SDCK rising edge
23
SDRAMC
SDWE high after SDCK rising edge
24
SDRAMC
D0-D15 Out valid before SDCK rising edge
25
SDRAMC
D0-D15 Out valid after SDCK rising edge
26
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
32117CS–AVR-08/11
Conditions
V
= 3.0V,
VDD
drive strength of the pads set to
the highest,
external capacitor = 40pF on
SDRAM pins
except 8 pF on SDCK pins
AT32UC3C
Min
Units
5.6
7.3
6.8
8.3
6.1
8.4
7
7.7
6.4
7.1
4.7
4.4
ns
6.2
6.9
6.6
7.8
6
6.7
6.4
0
7
7.4
5.2
5.6
85
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