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AT32UC3C064C
AT32UC3C064C | |
|---|---|
| Manufacturer Part Number | AT32UC3C064C |
| Manufacturer | Atmel Corporation |
| AT32UC3C064C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
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- If you still have any questions - please contact us
Specifications of AT32UC3C064C | |||
|---|---|---|---|
| Flash (kbytes) | 64 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 20 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
Figure 2-7.
B i t 1 5
R
T
0
0
SS - Secure State
This bit is indicates if the processor is executing in the secure state. For more details, see chap-
ter 4. The bit is initialized in an IMPLEMENTATION DEFINED way at reset.
H - Java Handle
This bit is included to support different heap types in the Java Virtual Machine. For more details,
see chapter 3. The bit is cleared at reset.
J - Java State
The processor is in Java state when this bit is set. The incoming instruction stream will be
decoded as a stream of Java bytecodes, not RISC opcodes. The bit is cleared at reset. This bit
should not be modified by the user as undefined behaviour may result.
DM - Debug State Mask
If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,
and can both be read and written by software.
D - Debug State
The processor is in debug state when this bit is set. The bit is cleared at reset and should only be
modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-
iour may result if the user tries to modify this bit manually.
M2, M1, M0 - Execution Mode
These bits show the active execution mode. The settings for the different modes are shown in
Table 2-5 on page
supervisor mode after reset. These bits are modified by hardware, or execution of certain
instructions like scall, rets and rete. Undefined behaviour may result if the user tries to modify
these bits manually.
AVR32
12
The Status Register low halfword
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
13. M2 and M1 are cleared by reset while M0 is set so that the processor is in
B i t 0
L
Q
V
N
Z
C
B it n a m e
0
0
0
0
0
0
In itia l v a lu e
C a r r y
Z e r o
S ig n
O v e r f lo w
S a tu r a tio n
L o c k
R e s e r v e d
S c r a tc h
R e g is te r R e m a p E n a b le
32000D–04/2011
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