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AT32UC3C064C
AT32UC3C064C | |
|---|---|
| Manufacturer Part Number | AT32UC3C064C |
| Manufacturer | Atmel Corporation |
| AT32UC3C064C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of AT32UC3C064C | |||
|---|---|---|---|
| Flash (kbytes) | 64 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 20 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
BREAKPOINT – Software Debug Breakpoint
Architecture revision:
Architecture revision1 and higher.
Description
If the on chip debug system is enabled, this instruction traps a software breakpoint for debugging. The breakpoint instruc-
tion will enter debug mode disabling all interrupts and exceptions. If the on chip debug system is not enabled, this
instruction will execute as a nop.
Operation:
I.
Syntax:
I.
Operands:
Status Flags:
Opcode:
15
1
Note:
If no on chip debug system is implemented, this instruction will execute as a "NOP".
32000D–04/2011
if (SR[DM]==0)
RSR_DBG ← SR;
RAR_DBG ← address of first non-completed instruction;
SR[R] ← 1;
SR[J] ← 1;
SR[D] ← 1;
SR[M2:M0] ← B’110;
SR[DM] ← 1;
SR[EM] ← 1;
SR[GM] ← 1;
PC ← EVBA+0x1C;
else
PC ← PC + 2;
breakpoint
None
Q:
Not affected.
V:
Not affected.
N:
Not affected.
Z:
Not affected.
C:
Not affected.
9
1
0
1
0
1
1
8
4
3
0
0
1
1
1
0
AVR32
0
0
1
1
145
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